[POWERPC] Separate IRQ config / register set from main header

There is no need to expose these settings outside the scope
of the interrupt controller code itself.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Paul Mackerras <paulus@samba.org>

diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
index 6df51f04b8f5025f780cb4318a710c462b5d735e..504154fdf6a6407d643328a3b80b4be3c6056a62 100644 (file)
--- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
@@ -33,6 +33,7 @@
 #include <asm/irq.h>
 #include <asm/prom.h>
 #include <asm/mpc52xx.h>
+#include "mpc52xx_pic.h"
 
 /*
  *

diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.h b/arch/powerpc/platforms/52xx/mpc52xx_pic.h
new file mode 100644 (file)
index 0000000..1a26bcd
--- /dev/null
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.h
@@ -0,0 +1,53 @@
+/*
+ * Header file for Freescale MPC52xx Interrupt controller
+ *
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __POWERPC_SYSDEV_MPC52xx_PIC_H__
+#define __POWERPC_SYSDEV_MPC52xx_PIC_H__
+
+#include <asm/types.h>
+
+
+/* HW IRQ mapping */
+#define MPC52xx_IRQ_L1_CRIT    (0)
+#define MPC52xx_IRQ_L1_MAIN    (1)
+#define MPC52xx_IRQ_L1_PERP    (2)
+#define MPC52xx_IRQ_L1_SDMA    (3)
+
+#define MPC52xx_IRQ_L1_OFFSET   (6)
+#define MPC52xx_IRQ_L1_MASK     (0x00c0)
+
+#define MPC52xx_IRQ_L2_OFFSET   (0)
+#define MPC52xx_IRQ_L2_MASK     (0x003f)
+
+#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
+
+
+/* Interrupt controller Register set */
+struct mpc52xx_intr {
+       u32 per_mask;           /* INTR + 0x00 */
+       u32 per_pri1;           /* INTR + 0x04 */
+       u32 per_pri2;           /* INTR + 0x08 */
+       u32 per_pri3;           /* INTR + 0x0c */
+       u32 ctrl;               /* INTR + 0x10 */
+       u32 main_mask;          /* INTR + 0x14 */
+       u32 main_pri1;          /* INTR + 0x18 */
+       u32 main_pri2;          /* INTR + 0x1c */
+       u32 reserved1;          /* INTR + 0x20 */
+       u32 enc_status;         /* INTR + 0x24 */
+       u32 crit_status;        /* INTR + 0x28 */
+       u32 main_status;        /* INTR + 0x2c */
+       u32 per_status;         /* INTR + 0x30 */
+       u32 reserved2;          /* INTR + 0x34 */
+       u32 per_error;          /* INTR + 0x38 */
+};
+
+#endif /* __POWERPC_SYSDEV_MPC52xx_PIC_H__ */
+

diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
index e9aa622f19f612c4a18f8e5f118fa9a62395c16d..fff752c4bd17abc254dfed1869b9465b85f1a399 100644 (file)
--- a/include/asm-powerpc/mpc52xx.h
+++ b/include/asm-powerpc/mpc52xx.h
@@ -19,49 +19,12 @@
 #endif /* __ASSEMBLY__ */
 
 
-/* ======================================================================== */
-/* HW IRQ mapping                                                           */
-/* ======================================================================== */
-
-#define MPC52xx_IRQ_L1_CRIT            (0)
-#define MPC52xx_IRQ_L1_MAIN            (1)
-#define MPC52xx_IRQ_L1_PERP            (2)
-#define MPC52xx_IRQ_L1_SDMA            (3)
-
-#define MPC52xx_IRQ_L1_OFFSET          (6)
-#define MPC52xx_IRQ_L1_MASK            (0xc0)
-
-#define MPC52xx_IRQ_L2_OFFSET          (0)
-#define MPC52xx_IRQ_L2_MASK            (0x3f)
-
-#define MPC52xx_IRQ_HIGHTESTHWIRQ      (0xd0)
-
-
 /* ======================================================================== */
 /* Structures mapping of some unit register set                             */
 /* ======================================================================== */
 
 #ifndef __ASSEMBLY__
 
-/* Interrupt controller Register set */
-struct mpc52xx_intr {
-       u32 per_mask;           /* INTR + 0x00 */
-       u32 per_pri1;           /* INTR + 0x04 */
-       u32 per_pri2;           /* INTR + 0x08 */
-       u32 per_pri3;           /* INTR + 0x0c */
-       u32 ctrl;               /* INTR + 0x10 */
-       u32 main_mask;          /* INTR + 0x14 */
-       u32 main_pri1;          /* INTR + 0x18 */
-       u32 main_pri2;          /* INTR + 0x1c */
-       u32 reserved1;          /* INTR + 0x20 */
-       u32 enc_status;         /* INTR + 0x24 */
-       u32 crit_status;        /* INTR + 0x28 */
-       u32 main_status;        /* INTR + 0x2c */
-       u32 per_status;         /* INTR + 0x30 */
-       u32 reserved2;          /* INTR + 0x34 */
-       u32 per_error;          /* INTR + 0x38 */
-};
-
 /* Memory Mapping Control */
 struct mpc52xx_mmap_ctl {
        u32 mbar;               /* MMAP_CTRL + 0x00 */