]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
pm2fb: Permedia 2V memory clock setting
authorKrzysztof Helt <krzysztof.h1@wp.pl>
Tue, 8 May 2007 07:39:32 +0000 (00:39 -0700)
committerLinus Torvalds <torvalds@woody.linux-foundation.org>
Tue, 8 May 2007 18:15:32 +0000 (11:15 -0700)
Permedia 2V uses its own registers to set a memory clock. The
patch adds these registers and uses them in the set_memclock()
function.

Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
Signed-off-by: Antonino Daplas <adaplas@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
drivers/video/pm2fb.c
include/video/permedia2.h

index 2c7dccbd52502a94f55771b944368e8410edf075..6f634e3ae60da882067db71786f7932cee48adce 100644 (file)
@@ -462,21 +462,43 @@ static void set_memclock(struct pm2fb_par* par, u32 clk)
        int i;
        unsigned char m, n, p;
 
-       pm2_mnp(clk, &m, &n, &p);
-       WAIT_FIFO(par, 10);
-       pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
-       wmb();
-       pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
-       pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
-       wmb();
-       pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
-       wmb();
-       pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
-       rmb();
-       for (i = 256;
-            i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
-            i--)
-               ;
+       switch (par->type) {
+       case PM2_TYPE_PERMEDIA2V:
+               pm2v_mnp(clk/2, &m, &n, &p);
+               WAIT_FIFO(par, 8);
+               pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
+               pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
+               wmb();
+               pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
+               pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
+               pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
+               wmb();
+               pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
+               rmb();
+               for (i = 256;
+                    i && !(pm2_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2);
+                    i--)
+                       ;
+               pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
+               break;
+       case PM2_TYPE_PERMEDIA2:
+               pm2_mnp(clk, &m, &n, &p);
+               WAIT_FIFO(par, 10);
+               pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
+               wmb();
+               pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
+               pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
+               wmb();
+               pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
+               wmb();
+               pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
+               rmb();
+               for (i = 256;
+                    i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
+                    i--)
+                       ;
+               break;
+       }
 }
 
 static void set_pixclock(struct pm2fb_par* par, u32 clk)
index b95d36289336711d69ad7edf76a213cdf25a6431..9e49c9571ec3b6d7d9c840ba8f30f4e431c733c3 100644 (file)
 #define PM2VI_RD_CLK1_PRESCALE                         0x204
 #define PM2VI_RD_CLK1_FEEDBACK                         0x205
 #define PM2VI_RD_CLK1_POSTSCALE                                0x206
+#define PM2VI_RD_MCLK_CONTROL                          0x20D
+#define PM2VI_RD_MCLK_PRESCALE                         0x20E
+#define PM2VI_RD_MCLK_FEEDBACK                         0x20F
+#define PM2VI_RD_MCLK_POSTSCALE                                0x210
 #define PM2VI_RD_CURSOR_PALETTE                                0x303
 #define PM2VI_RD_CURSOR_PATTERN                                0x400