/* REVISIT make this an error later once the same driver code works
* with the Mentor DMA engine too
*/
- if (otgCh->pEndPt)
+ if (otgCh->hw_ep)
DBG(1, "re-allocating DMA%d %cX channel %p\n",
chNum, bTransmit ? 'T' : 'R', otgCh);
- otgCh->pEndPt = ep;
+ otgCh->hw_ep = ep;
otgCh->Channel.bStatus = MGC_DMA_STATUS_FREE;
DBG(4, "Allocate CPPI%d %cX\n", chNum, bTransmit ? 'T' : 'R');
c = container_of(channel, struct cppi_channel, Channel);
epnum = c->chNo + 1;
tibase = c->pController->pCoreBase - DAVINCI_BASE_OFFSET;
- if (!c->pEndPt)
+ if (!c->hw_ep)
DBG(1, "releasing idle DMA channel %p\n", c);
else if (!c->bTransmit)
core_rxirq_enable(tibase, epnum);
/* for now, leave its cppi IRQ enabled (we won't trigger it) */
- c->pEndPt = NULL;
+ c->hw_ep = NULL;
channel->bStatus = MGC_DMA_STATUS_UNKNOWN;
}
c->chNo, tag,
musb_readl(base - DAVINCI_BASE_OFFSET,
DAVINCI_RXCPPI_BUFCNT0_REG + 4 *c->chNo),
- musb_readw(c->pEndPt->regs, MGC_O_HDRC_RXCSR),
+ musb_readw(c->hw_ep->regs, MGC_O_HDRC_RXCSR),
musb_readl(c->stateRam, 0 * 4), /* buf offset */
musb_readl(c->stateRam, 1 * 4), /* head ptr */
"F%08x L%08x .. %08x"
"\n",
c->chNo, tag,
- musb_readw(c->pEndPt->regs, MGC_O_HDRC_TXCSR),
+ musb_readw(c->hw_ep->regs, MGC_O_HDRC_TXCSR),
musb_readl(c->stateRam, 0 * 4), /* head ptr */
musb_readl(c->stateRam, 1 * 4), /* sop bd */
/* REQPKT is turned off after each segment */
if (n_bds && rx->actualLen) {
- void *__iomem regs = rx->pEndPt->regs;
+ void *__iomem regs = rx->hw_ep->regs;
val = musb_readw(regs, MGC_O_HDRC_RXCSR);
if (!(val & MGC_M_RXCSR_H_REQPKT)) {
int completed = 0, acked = 0;
int i;
dma_addr_t safe2ack;
- void *__iomem regs = rx->pEndPt->regs;
+ void *__iomem regs = rx->hw_ep->regs;
cppi_dump_rx(6, rx, "/K");
/* REVISIT seems like "autoreq all but EOP" doesn't...
* setting it here "should" be racey, but seems to work
*/
- csr = musb_readw(rx->pEndPt->regs, MGC_O_HDRC_RXCSR);
+ csr = musb_readw(rx->hw_ep->regs, MGC_O_HDRC_RXCSR);
if (is_host_active(cppi->musb)
&& bd
&& !(csr & MGC_M_RXCSR_H_REQPKT)) {
csr |= MGC_M_RXCSR_H_REQPKT;
musb_writew(regs, MGC_O_HDRC_RXCSR,
MGC_M_RXCSR_H_WZC_BITS | csr);
- csr = musb_readw(rx->pEndPt->regs, MGC_O_HDRC_RXCSR);
+ csr = musb_readw(rx->hw_ep->regs, MGC_O_HDRC_RXCSR);
}
} else {
rx->activeQueueHead = NULL;
txChannel->Channel.bStatus =
MGC_DMA_STATUS_FREE;
- pEnd = txChannel->pEndPt;
+ pEnd = txChannel->hw_ep;
txChannel->Channel.dwActualLength =
txChannel->actualLen;
/* all segments completed! */
rxChannel->Channel.bStatus = MGC_DMA_STATUS_FREE;
- pEnd = rxChannel->pEndPt;
+ pEnd = rxChannel->hw_ep;
rxChannel->Channel.dwActualLength =
rxChannel->actualLen;
/* from RX or TX fault irq handler */
case MGC_DMA_STATUS_BUSY:
/* the hardware needs shutting down */
- regs = otgCh->pEndPt->regs;
+ regs = otgCh->hw_ep->regs;
break;
case MGC_DMA_STATUS_UNKNOWN:
case MGC_DMA_STATUS_FREE: