Fix some base address declaration by adding a cast.
Signed-off-by: Luotao Fu <l.fu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*/
int mxc_iomux_mode(unsigned int pin_mode)
{
- u32 reg, field, l, mode, ret = 0;
+ u32 field, l, mode, ret = 0;
+ void __iomem *reg;
reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
field = pin_mode & 0x3;
*/
void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
{
- u32 reg, field, l;
+ u32 field, l;
+ void __iomem *reg;
reg = IOMUXSW_PAD_CTL + (pin + 2) / 3;
field = (pin + 2) % 3;
/* Register bit position for clock's enable/disable control. */
u8 enable_shift;
/* Register address for clock's enable/disable control. */
- u32 enable_reg;
+ void __iomem *enable_reg;
u32 flags;
/* get the current clock rate (always a fresh value) */
unsigned long (*get_rate) (struct clk *);
* it returns 0xDEADBEEF
*/
#define IO_ADDRESS(x) \
+ (void __iomem *) \
(((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
AIPI_IO_ADDRESS(x) : \
((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
* it returns 0xDEADBEEF
*/
#define IO_ADDRESS(x) \
+ (void __iomem *) \
(((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\