#define MUSB_DEVCTL_FSDEV 0x40
#define MUSB_DEVCTL_LSDEV 0x20
#define MUSB_DEVCTL_VBUS 0x18
-#define MGC_S_DEVCTL_VBUS 3
+#define MUSB_DEVCTL_VBUS_SHIFT 3
#define MUSB_DEVCTL_HM 0x04
#define MUSB_DEVCTL_HR 0x02
#define MUSB_DEVCTL_SESSION 0x01
/* TxType/RxType */
#define MUSB_TYPE_SPEED 0xc0
-#define MGC_S_TYPE_SPEED 6
+#define MUSB_TYPE_SPEED_SHIFT 6
#define MGC_TYPE_SPEED_HIGH 1
#define MGC_TYPE_SPEED_FULL 2
#define MGC_TYPE_SPEED_LOW 3
#define MUSB_TYPE_PROTO 0x30 /* implicitly zero for ep0 */
-#define MGC_S_TYPE_PROTO 4
+#define MUSB_TYPE_PROTO_SHIFT 4
#define MUSB_TYPE_REMOTE_END 0xf /* implicitly zero for ep0 */
/* CONFIGDATA */
(MGC_O_HSDMA_BASE + (_bChannel << 4) + _bOffset)
/* control register (16-bit): */
-#define MGC_S_HSDMA_ENABLE 0
-#define MGC_S_HSDMA_TRANSMIT 1
-#define MGC_S_HSDMA_MODE1 2
-#define MGC_S_HSDMA_IRQENABLE 3
-#define MGC_S_HSDMA_ENDPOINT 4
-#define MGC_S_HSDMA_BUSERROR 8
-#define MGC_S_HSDMA_BURSTMODE 9
-#define MUSB_HSDMA_BURSTMODE (3 << MGC_S_HSDMA_BURSTMODE)
+#define MUSB_HSDMA_ENABLE_SHIFT 0
+#define MUSB_HSDMA_TRANSMIT_SHIFT 1
+#define MUSB_HSDMA_MODE1_SHIFT 2
+#define MUSB_HSDMA_IRQENABLE_SHIFT 3
+#define MUSB_HSDMA_ENDPOINT_SHIFT 4
+#define MUSB_HSDMA_BUSERROR_SHIFT 8
+#define MUSB_HSDMA_BURSTMODE_SHIFT 9
+#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
#define MGC_HSDMA_BURSTMODE_UNSPEC 0
#define MGC_HSDMA_BURSTMODE_INCR4 1
#define MGC_HSDMA_BURSTMODE_INCR8 2
pChannel, packet_sz, dma_addr, dwLength, mode);
if (mode) {
- wCsr |= 1 << MGC_S_HSDMA_MODE1;
+ wCsr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
if (dwLength < packet_sz) {
return FALSE;
}
if (packet_sz >= 64) {
wCsr |=
- MGC_HSDMA_BURSTMODE_INCR16 << MGC_S_HSDMA_BURSTMODE;
+ MGC_HSDMA_BURSTMODE_INCR16 << MUSB_HSDMA_BURSTMODE_SHIFT;
} else if (packet_sz >= 32) {
wCsr |=
- MGC_HSDMA_BURSTMODE_INCR8 << MGC_S_HSDMA_BURSTMODE;
+ MGC_HSDMA_BURSTMODE_INCR8 << MUSB_HSDMA_BURSTMODE_SHIFT;
} else if (packet_sz >= 16) {
wCsr |=
- MGC_HSDMA_BURSTMODE_INCR4 << MGC_S_HSDMA_BURSTMODE;
+ MGC_HSDMA_BURSTMODE_INCR4 << MUSB_HSDMA_BURSTMODE_SHIFT;
}
}
- wCsr |= (pImplChannel->epnum << MGC_S_HSDMA_ENDPOINT)
- | (1 << MGC_S_HSDMA_ENABLE)
- | (1 << MGC_S_HSDMA_IRQENABLE)
- | (pImplChannel->bTransmit ? (1 << MGC_S_HSDMA_TRANSMIT) : 0);
+ wCsr |= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
+ | (1 << MUSB_HSDMA_ENABLE_SHIFT)
+ | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
+ | (pImplChannel->bTransmit ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) : 0);
/* address/count */
musb_writel(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel,
MGC_O_HSDMA_CONTROL));
- if (wCsr & (1 << MGC_S_HSDMA_BUSERROR)) {
+ if (wCsr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
pImplChannel->Channel.status =
MGC_DMA_STATUS_BUS_ABORT;
} else {
* not get a disconnect irq...
*/
if ((devctl & MUSB_DEVCTL_VBUS)
- != (3 << MGC_S_DEVCTL_VBUS)) {
+ != (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
musb->int_usb |= MUSB_INTR_DISCONNECT;
musb->int_usb &= ~MUSB_INTR_SUSPEND;
break;
devctl,
({ char *s;
switch (devctl & MUSB_DEVCTL_VBUS) {
- case 0 << MGC_S_DEVCTL_VBUS:
+ case 0 << MUSB_DEVCTL_VBUS_SHIFT:
s = "<SessEnd"; break;
- case 1 << MGC_S_DEVCTL_VBUS:
+ case 1 << MUSB_DEVCTL_VBUS_SHIFT:
s = "<AValid"; break;
- case 2 << MGC_S_DEVCTL_VBUS:
+ case 2 << MUSB_DEVCTL_VBUS_SHIFT:
s = "<VBusValid"; break;
- //case 3 << MGC_S_DEVCTL_VBUS:
+ //case 3 << MUSB_DEVCTL_VBUS_SHIFT:
default:
s = "VALID"; break;
}; s; }),
break;
default:
if ((devctl & MUSB_DEVCTL_VBUS)
- == (3 << MGC_S_DEVCTL_VBUS)) {
+ == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
musb->xceiv.state = OTG_STATE_A_HOST;
hcd->self.is_b_host = 0;
}