*       new packet type)
  * 1.26- Add support for variable size PCI(E) gart aperture
  * 1.27- Add support for IGP GART
+ * 1.28- Add support for VBL on CRTC2
  */
 #define DRIVER_MAJOR           1
-#define DRIVER_MINOR           27
+#define DRIVER_MINOR           28
 #define DRIVER_PATCHLEVEL      0
 
 /*
        /* SW interrupt */
        wait_queue_head_t swi_queue;
        atomic_t swi_emitted;
+       int vblank_crtc;
+       uint32_t irq_enable_reg;
+       int irq_enabled;
 
        struct radeon_surface surfaces[RADEON_MAX_SURFACES];
        struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
 extern void radeon_do_release(drm_device_t * dev);
 extern int radeon_driver_vblank_wait(drm_device_t * dev,
                                     unsigned int *sequence);
+extern int radeon_driver_vblank_wait2(drm_device_t * dev,
+                                     unsigned int *sequence);
 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
 extern void radeon_driver_irq_preinstall(drm_device_t * dev);
 extern void radeon_driver_irq_postinstall(drm_device_t * dev);
 extern void radeon_driver_irq_uninstall(drm_device_t * dev);
+extern int radeon_vblank_crtc_get(drm_device_t *dev);
+extern int radeon_vblank_crtc_set(drm_device_t *dev, int64_t value);
 
 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
 extern int radeon_driver_unload(struct drm_device *dev);
 
 #define RADEON_GEN_INT_CNTL            0x0040
 #      define RADEON_CRTC_VBLANK_MASK          (1 << 0)
+#      define RADEON_CRTC2_VBLANK_MASK         (1 << 9)
 #      define RADEON_GUI_IDLE_INT_ENABLE       (1 << 19)
 #      define RADEON_SW_INT_ENABLE             (1 << 25)
 
 #define RADEON_GEN_INT_STATUS          0x0044
 #      define RADEON_CRTC_VBLANK_STAT          (1 << 0)
 #      define RADEON_CRTC_VBLANK_STAT_ACK      (1 << 0)
+#      define RADEON_CRTC2_VBLANK_STAT         (1 << 9)
+#      define RADEON_CRTC2_VBLANK_STAT_ACK     (1 << 9)
 #      define RADEON_GUI_IDLE_INT_TEST_ACK     (1 << 19)
 #      define RADEON_SW_INT_TEST               (1 << 25)
 #      define RADEON_SW_INT_TEST_ACK           (1 << 25)
 
         * outside the DRM
         */
        stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
-                                                 RADEON_CRTC_VBLANK_STAT));
+                                                 RADEON_CRTC_VBLANK_STAT |
+                                                 RADEON_CRTC2_VBLANK_STAT));
        if (!stat)
                return IRQ_NONE;
 
+       stat &= dev_priv->irq_enable_reg;
+
        /* SW interrupt */
        if (stat & RADEON_SW_INT_TEST) {
                DRM_WAKEUP(&dev_priv->swi_queue);
        }
 
        /* VBLANK interrupt */
-       if (stat & RADEON_CRTC_VBLANK_STAT) {
-               atomic_inc(&dev->vbl_received);
+       if (stat & (RADEON_CRTC_VBLANK_STAT|RADEON_CRTC2_VBLANK_STAT)) {
+               int vblank_crtc = dev_priv->vblank_crtc;
+
+               if ((vblank_crtc &
+                    (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) ==
+                   (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
+                       if (stat & RADEON_CRTC_VBLANK_STAT)
+                               atomic_inc(&dev->vbl_received);
+                       if (stat & RADEON_CRTC2_VBLANK_STAT)
+                               atomic_inc(&dev->vbl_received2);
+               } else if (((stat & RADEON_CRTC_VBLANK_STAT) &&
+                          (vblank_crtc & DRM_RADEON_VBLANK_CRTC1)) ||
+                          ((stat & RADEON_CRTC2_VBLANK_STAT) &&
+                           (vblank_crtc & DRM_RADEON_VBLANK_CRTC2)))
+                       atomic_inc(&dev->vbl_received);
+
                DRM_WAKEUP(&dev->vbl_queue);
                drm_vbl_send_signals(dev);
        }
        return ret;
 }
 
-int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
+int radeon_driver_vblank_do_wait(drm_device_t * dev, unsigned int *sequence,
+                                int crtc)
 {
        drm_radeon_private_t *dev_priv =
            (drm_radeon_private_t *) dev->dev_private;
        unsigned int cur_vblank;
        int ret = 0;
-
+       int ack = 0;
+       atomic_t *counter;
        if (!dev_priv) {
                DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
                return DRM_ERR(EINVAL);
        }
 
-       radeon_acknowledge_irqs(dev_priv, RADEON_CRTC_VBLANK_STAT);
+       if (crtc == DRM_RADEON_VBLANK_CRTC1) {
+               counter = &dev->vbl_received;
+               ack |= RADEON_CRTC_VBLANK_STAT;
+       } else if (crtc == DRM_RADEON_VBLANK_CRTC2) {
+               counter = &dev->vbl_received2;
+               ack |= RADEON_CRTC2_VBLANK_STAT;
+       } else
+               return DRM_ERR(EINVAL);
+
+       radeon_acknowledge_irqs(dev_priv, ack);
 
        dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 
         * using vertical blanks...
         */
        DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
-                   (((cur_vblank = atomic_read(&dev->vbl_received))
+                   (((cur_vblank = atomic_read(counter))
                      - *sequence) <= (1 << 23)));
 
        *sequence = cur_vblank;
        return ret;
 }
 
+int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
+{
+       return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC1);
+}
+
+int radeon_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence)
+{
+       return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC2);
+}
+
 /* Needs the lock as it touches the ring.
  */
 int radeon_irq_emit(DRM_IOCTL_ARGS)
        return radeon_wait_irq(dev, irqwait.irq_seq);
 }
 
+static void radeon_enable_interrupt(drm_device_t *dev)
+{
+       drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
+
+       dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
+       if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1)
+               dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
+
+       if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2)
+               dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
+
+       RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
+       dev_priv->irq_enabled = 1;
+}
+
 /* drm_dma.h hooks
 */
 void radeon_driver_irq_preinstall(drm_device_t * dev)
 
        /* Clear bits if they're already high */
        radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
-                                          RADEON_CRTC_VBLANK_STAT));
+                                          RADEON_CRTC_VBLANK_STAT |
+                                          RADEON_CRTC2_VBLANK_STAT));
 }
 
 void radeon_driver_irq_postinstall(drm_device_t * dev)
        atomic_set(&dev_priv->swi_emitted, 0);
        DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 
-       /* Turn on SW and VBL ints */
-       RADEON_WRITE(RADEON_GEN_INT_CNTL,
-                    RADEON_CRTC_VBLANK_MASK | RADEON_SW_INT_ENABLE);
+       radeon_enable_interrupt(dev);
 }
 
 void radeon_driver_irq_uninstall(drm_device_t * dev)
        if (!dev_priv)
                return;
 
+       dev_priv->irq_enabled = 0;
+
        /* Disable *all* interrupts */
        RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 }
+
+
+int radeon_vblank_crtc_get(drm_device_t *dev)
+{
+       drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
+       u32 flag;
+       u32 value;
+
+       flag = RADEON_READ(RADEON_GEN_INT_CNTL);
+       value = 0;
+
+       if (flag & RADEON_CRTC_VBLANK_MASK)
+               value |= DRM_RADEON_VBLANK_CRTC1;
+
+       if (flag & RADEON_CRTC2_VBLANK_MASK)
+               value |= DRM_RADEON_VBLANK_CRTC2;
+       return value;
+}
+
+int radeon_vblank_crtc_set(drm_device_t *dev, int64_t value)
+{
+       drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
+       if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
+               DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
+               return DRM_ERR(EINVAL);
+       }
+       dev_priv->vblank_crtc = (unsigned int)value;
+       radeon_enable_interrupt(dev);
+       return 0;
+}