PIIX_80C_SEC = (1 << 7) | (1 << 6),
/* controller IDs */
- piix4_pata = 0,
- ich5_pata = 1,
- ich5_sata = 2,
- esb_sata = 3,
- ich6_sata = 4,
- ich6_sata_ahci = 5,
- ich6m_sata_ahci = 6,
- ich7m_sata_ahci = 7,
- ich8_sata_ahci = 8,
+ piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */
+ ich_pata_33 = 1, /* ICH up to UDMA 33 only */
+ ich_pata_66 = 2, /* ICH up to 66 Mhz */
+ ich_pata_100 = 3, /* ICH up to UDMA 100 */
+ ich_pata_133 = 4, /* ICH up to UDMA 133 */
+ ich5_sata = 5,
+ esb_sata = 6,
+ ich6_sata = 7,
+ ich6_sata_ahci = 8,
+ ich6m_sata_ahci = 9,
- ich8_sata_ahci = 10,
++ ich7m_sata_ahci = 10,
++ ich8_sata_ahci = 11,
/* constants for mapping table */
P0 = 0, /* port 0 */
.port_ops = &piix_sata_ops,
},
- /* ich6_sata_ahci:8 */
- /* ich6_sata_ahci */
++ /* ich6_sata_ahci: 8 */
{
.sht = &piix_sht,
- .host_flags = ATA_FLAG_SATA |
+ .flags = ATA_FLAG_SATA |
PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
PIIX_FLAG_AHCI,
.pio_mask = 0x1f, /* pio0-4 */
.port_ops = &piix_sata_ops,
},
- /* ich8_sata_ahci */
- /* ich7m_sata_ahci */
++ /* ich7m_sata_ahci: 10 */
+ {
+ .sht = &piix_sht,
+ .host_flags = ATA_FLAG_SATA |
+ PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
+ PIIX_FLAG_AHCI,
+ .pio_mask = 0x1f, /* pio0-4 */
+ .mwdma_mask = 0x07, /* mwdma0-2 */
+ .udma_mask = 0x7f, /* udma0-6 */
+ .port_ops = &piix_sata_ops,
+ },
+
- /* ich8_sata_ahci */
++ /* ich8_sata_ahci: 11 */
{
.sht = &piix_sht,
- .host_flags = ATA_FLAG_SATA |
+ .flags = ATA_FLAG_SATA |
PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
PIIX_FLAG_AHCI,
.pio_mask = 0x1f, /* pio0-4 */