GPIO: OMAP: Fixed spurious IRQ issue for GPIO interrupts

Flush posted write to IRQSTATUS register in GPIO IRQ handler.
This eliminates the below error for all peripherals that use GPIO interrupts.

<4>Spurious irq 95: 0xffffffdf, please flush posted write for irq 31

Signed-off-by: Roger Quadros <ext-roger.quadros@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 210a1c04555488cf9d4d39856557b9caac029b53..17d7afe42b83efce507a8112af98d4de8280d02a 100644 (file)
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -758,8 +758,12 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 
        /* Workaround for clearing DSP GPIO interrupts to allow retention */
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+       reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-               __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
+               __raw_writel(gpio_mask, reg);
+
+       /* Flush posted write for the irq status to avoid spurious interrupts */
+       __raw_readl(reg);
 #endif
 }