* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+#undef DEBUG
+
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>
#include <linux/module.h>
+#include <linux/io.h>
-#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/arch/gpmc.h>
-#undef DEBUG
-
-#if defined(CONFIG_ARCH_OMAP2420)
-#define GPMC_BASE 0x6800a000
-#elif defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
-#define GPMC_BASE 0x6e000000
-#endif
+#include "memory.h"
+/* GPMC register offsets */
#define GPMC_REVISION 0x00
#define GPMC_SYSCONFIG 0x10
#define GPMC_SYSSTATUS 0x14
static DEFINE_SPINLOCK(gpmc_mem_lock);
static unsigned gpmc_cs_map;
-static void __iomem *gpmc_base =
- (void __iomem *) IO_ADDRESS(GPMC_BASE);
-static void __iomem *gpmc_cs_base =
- (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
+static u32 gpmc_base;
static struct clk *gpmc_l3_clk;
static void gpmc_write_reg(int idx, u32 val)
{
- __raw_writel(val, gpmc_base + idx);
+ omap_writel(val, gpmc_base + idx);
}
static u32 gpmc_read_reg(int idx)
{
- return __raw_readl(gpmc_base + idx);
+ return omap_readl(gpmc_base + idx);
}
void gpmc_cs_write_reg(int cs, int idx, u32 val)
{
- void __iomem *reg_addr;
+ u32 reg_addr;
- reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
- __raw_writel(val, reg_addr);
+ reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
+ omap_writel(val, reg_addr);
}
u32 gpmc_cs_read_reg(int cs, int idx)
{
- return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
+ return omap_readl(gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx);
}
/* TODO: Add support for gpmc_fck to clock framework and use it */
}
EXPORT_SYMBOL(gpmc_cs_free);
-void __init gpmc_mem_init(void)
+static void __init gpmc_mem_init(void)
{
int cs;
unsigned long boot_rom_space = 0;
{
u32 l;
- if (cpu_is_omap24xx())
+ if (cpu_is_omap24xx()) {
gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
- else if (cpu_is_omap34xx())
+ if (cpu_is_omap2420())
+ gpmc_base = OMAP2420_GPMC_BASE;
+ else if (cpu_is_omap2430())
+ gpmc_base = OMAP243X_GPMC_BASE;
+ } else if (cpu_is_omap34xx()) {
gpmc_l3_clk = clk_get(NULL, "gpmc_fck");
+ gpmc_base = OMAP34XX_GPMC_BASE;
+ }
BUG_ON(IS_ERR(gpmc_l3_clk));
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/io.h>
#include <asm/tlb.h>
-#include <asm/io.h>
#include <asm/mach/map.h>
-
#include <asm/arch/mux.h>
#include <asm/arch/omapfb.h>
+#include <asm/arch/sram.h>
+
+#include "memory.h"
+
+#include "clock.h"
#include <asm/arch/powerdomain.h>
#include <asm/arch/clockdomain.h>
#include "clockdomains.h"
-extern void omap_sram_init(void);
-extern int omap2_clk_init(void);
extern void omap2_check_revision(void);
-extern void omap2_init_memory(void);
-extern void gpmc_init(void);
extern void omapfb_reserve_sdram(void);
/*
static void __attribute__((unused)) sdrc_write_reg(u32 val, u16 reg)
{
pr_debug("sdrc_write_reg: writing 0x%0x to 0x%0x\n", val,
- (u32)OMAP_SDRC_REGADDR(reg));
+ (__force u32)OMAP_SDRC_REGADDR(reg));
__raw_writel(val, OMAP_SDRC_REGADDR(reg));
}
static void __attribute__((unused)) sms_write_reg(u32 val, u16 reg)
{
pr_debug("sms_write_reg: writing 0x%0x to 0x%0x\n", val,
- (u32)OMAP_SMS_REGADDR(reg));
+ (__force u32)OMAP_SMS_REGADDR(reg));
__raw_writel(val, OMAP_SMS_REGADDR(reg));
}