DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value));
DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate));
DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate));
+#ifdef CONFIG_ARM_XENON
+ DEFINE(TI_XENONSTATE, offsetof(struct thread_info, xenonstate));
+#endif
#ifdef CONFIG_IWMMXT
DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt));
#endif
add ip, r1, #TI_CPU_SAVE
ldr r3, [r2, #TI_TP_VALUE]
stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
+#ifdef CONFIG_ARM_XENON
+ mrc p14, 6, r4, c1, c0, 0 @ current xenon state
+ ldr r5, [r2, #TI_XENONSTATE] @ value to restore
+ str r4, [r1, #TI_XENONSTATE] @ save current
+ mcr p14, 6, r5, c1, c0, 0 @ restore new value
+#endif
#ifdef CONFIG_MMU
ldr r6, [r2, #TI_CPU_DOMAIN]
#endif
If you don't know what this all is, saying Y is a safe choice.
+config ARM_XENON
+ bool "Enable Xenon extension"
+ depends on CPU_V7
+ help
+ Say Y here if you have a CPU with Xenon extension and code to make
+ use of it. Say N for code that can run on CPUs without Xenon.
+
config CPU_BIG_ENDIAN
bool "Build big-endian kernel"
depends on ARCH_SUPPORTS_BIG_ENDIAN
struct crunch_state crunchstate;
union fp_state fpstate __attribute__((aligned(8)));
union vfp_state vfpstate;
+#ifdef CONFIG_ARM_XENON
+ unsigned long xenonstate; /* Jazelle-X handler base register */
+#endif
struct restart_block restart_block;
};