c->Channel.bStatus = MGC_DMA_STATUS_UNKNOWN;
c->pController = cppi;
c->bLastModeRndis = 0;
- c->Channel.pPrivateData = c;
+ c->Channel.private_data = c;
c->bdPoolHead = NULL;
/* build the BD Free list for the channel */
otgCh->Channel.bStatus = MGC_DMA_STATUS_FREE;
DBG(4, "Allocate CPPI%d %cX\n", chNum, bTransmit ? 'T' : 'R');
- otgCh->Channel.pPrivateData = otgCh;
+ otgCh->Channel.private_data = otgCh;
return &otgCh->Channel;
}
u16 wPacketSz, u8 mode,
dma_addr_t dma_addr, u32 dwLength)
{
- struct cppi_channel *otgChannel = pChannel->pPrivateData;
+ struct cppi_channel *otgChannel = pChannel->private_data;
struct cppi *pController = otgChannel->pController;
struct musb *musb = pController->musb;
/* Initialize the Cppi DmaController structure */
pController->pCoreBase = pCoreBase;
pController->musb = musb;
- pController->Controller.pPrivateData = pController;
+ pController->Controller.private_data = pController;
pController->Controller.start = cppi_controller_start;
pController->Controller.stop = cppi_controller_stop;
pController->Controller.channel_alloc = cppi_channel_allocate;
/**
* struct dma_channel - A DMA channel.
- * @pPrivateData: channel-private data
+ * @private_data: channel-private data
* @wMaxLength: the maximum number of bytes the channel can move in one
* transaction (typically representing many USB maximum-sized packets)
* @dwActualLength: how many bytes have been transferred
* one usb transfer.
*/
struct dma_channel {
- void *pPrivateData;
+ void *private_data;
// FIXME not void* private_data, but a dma_controller *
size_t dwMaxLength;
size_t dwActualLength;
/**
* struct dma_controller - A DMA Controller.
- * @pPrivateData: controller-private data;
+ * @private_data: controller-private data;
* @start: call this to start a DMA controller;
* return 0 on success, else negative errno
* @stop: call this to stop a DMA controller
* Controllers manage dma channels.
*/
struct dma_controller {
- void *pPrivateData;
+ void *private_data;
int (*start)(struct dma_controller *);
int (*stop)(struct dma_controller *);
struct dma_channel *(*channel_alloc)(struct dma_controller *,
pImplChannel->epnum = hw_ep->epnum;
pImplChannel->bTransmit = bTransmit;
pChannel = &(pImplChannel->Channel);
- pChannel->pPrivateData = pImplChannel;
+ pChannel->private_data = pImplChannel;
pChannel->bStatus = MGC_DMA_STATUS_FREE;
pChannel->dwMaxLength = 0x10000;
/* Tx => mode 1; Rx => mode 0 */
static void dma_channel_release(struct dma_channel *pChannel)
{
struct musb_dma_channel *pImplChannel =
- (struct musb_dma_channel *) pChannel->pPrivateData;
+ (struct musb_dma_channel *) pChannel->private_data;
pChannel->dwActualLength = 0;
pImplChannel->dwStartAddress = 0;
dma_addr_t dma_addr, u32 dwLength)
{
struct musb_dma_channel *pImplChannel =
- (struct musb_dma_channel *) pChannel->pPrivateData;
+ (struct musb_dma_channel *) pChannel->private_data;
struct musb_dma_controller *pController = pImplChannel->pController;
u8 *mbase = pController->pCoreBase;
u8 bChannel = pImplChannel->bIndex;
dma_addr_t dma_addr, u32 dwLength)
{
struct musb_dma_channel *pImplChannel =
- (struct musb_dma_channel *) pChannel->pPrivateData;
+ (struct musb_dma_channel *) pChannel->private_data;
DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
pImplChannel->epnum,
static int dma_channel_abort(struct dma_channel *pChannel)
{
struct musb_dma_channel *pImplChannel =
- (struct musb_dma_channel *) pChannel->pPrivateData;
+ (struct musb_dma_channel *) pChannel->private_data;
u8 bChannel = pImplChannel->bIndex;
u8 *mbase = pImplChannel->pController->pCoreBase;
u16 csr;
return 0;
}
-static irqreturn_t dma_controller_irq(int irq, void *pPrivateData)
+static irqreturn_t dma_controller_irq(int irq, void *private_data)
{
struct musb_dma_controller *pController =
- (struct musb_dma_controller *)pPrivateData;
+ (struct musb_dma_controller *)private_data;
struct musb_dma_channel *pImplChannel;
u8 *mbase = pController->pCoreBase;
struct dma_channel *pChannel;
void dma_controller_destroy(struct dma_controller *c)
{
struct musb_dma_controller *pController =
- (struct musb_dma_controller *) c->pPrivateData;
+ (struct musb_dma_controller *) c->private_data;
if (!pController)
return;
free_irq(pController->irq, c);
kfree(pController);
- c->pPrivateData = NULL;
+ c->private_data = NULL;
}
struct dma_controller *__init
pController->pDmaPrivate = musb;
pController->pCoreBase = pCoreBase;
- pController->Controller.pPrivateData = pController;
+ pController->Controller.private_data = pController;
pController->Controller.start = dma_controller_start;
pController->Controller.stop = dma_controller_stop;
pController->Controller.channel_alloc = dma_channel_allocate;
if (is_dma_capable() && musb->dma_controller) {
struct dma_controller *c = musb->dma_controller;
- (void) c->stop(c->pPrivateData);
+ (void) c->stop(c->private_data);
dma_controller_destroy(c);
}
c = dma_controller_create(musb, musb->mregs);
musb->dma_controller = c;
if (c)
- (void) c->start(c->pPrivateData);
+ (void) c->start(c->private_data);
}
#endif
/* ideally this would be abstracted in platform setup */
#define dmareq_works() 1
#endif
-#define to_chdat(c) (struct tusb_omap_dma_ch *)(c)->pPrivateData
+#define to_chdat(c) (struct tusb_omap_dma_ch *)(c)->private_data
#define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */
if (ch->bStatus == MGC_DMA_STATUS_UNKNOWN) {
ch->bStatus = MGC_DMA_STATUS_FREE;
channel = ch;
- chdat = ch->pPrivateData;
+ chdat = ch->private_data;
break;
}
}
for (i = 0; i < MAX_DMAREQ; i++) {
struct dma_channel *ch = dma_channel_pool[i];
if (ch) {
- if (ch->pPrivateData)
- kfree(ch->pPrivateData);
+ if (ch->private_data)
+ kfree(ch->private_data);
kfree(ch);
}
}
tusb_dma->controller.channel_release = tusb_omap_dma_release;
tusb_dma->controller.channel_program = tusb_omap_dma_program;
tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
- tusb_dma->controller.pPrivateData = tusb_dma;
+ tusb_dma->controller.private_data = tusb_dma;
for (i = 0; i < MAX_DMAREQ; i++) {
struct dma_channel *ch;
goto cleanup;
ch->bStatus = MGC_DMA_STATUS_UNKNOWN;
- ch->pPrivateData = chdat;
+ ch->private_data = chdat;
}
return &tusb_dma->controller;