static int last_cpu;
int cpu = last_cpu + 1;
- if (!irq_desc[irq].handler->set_affinity || irq_user_affinity[irq])
+ if (!irq_desc[irq].chip->set_affinity || irq_user_affinity[irq])
return 1;
while (!cpu_possible(cpu))
last_cpu = cpu;
irq_affinity[irq] = cpumask_of_cpu(cpu);
- irq_desc[irq].handler->set_affinity(irq, cpumask_of_cpu(cpu));
+ irq_desc[irq].chip->set_affinity(irq, cpumask_of_cpu(cpu));
return 0;
}
#endif /* CONFIG_SMP */
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_cpu(j).irqs[irq]);
#endif
- seq_printf(p, " %14s", irq_desc[irq].handler->typename);
+ seq_printf(p, " %14s", irq_desc[irq].chip->typename);
seq_printf(p, " %c%s",
(action->flags & SA_INTERRUPT)?'+':' ',
action->name);
init_rtc_irq(void)
{
irq_desc[RTC_IRQ].status = IRQ_DISABLED;
- irq_desc[RTC_IRQ].handler = &rtc_irq_type;
+ irq_desc[RTC_IRQ].chip = &rtc_irq_type;
setup_irq(RTC_IRQ, &timer_irqaction);
}
for (i = 0; i < 16; i++) {
irq_desc[i].status = IRQ_DISABLED;
- irq_desc[i].handler = &i8259a_irq_type;
+ irq_desc[i].chip = &i8259a_irq_type;
}
setup_irq(2, &cascade);
if ((ignore_mask >> i) & 1)
continue;
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = &pyxis_irq_type;
+ irq_desc[i].chip = &pyxis_irq_type;
}
setup_irq(16+7, &isa_cascade_irqaction);
if (i < 64 && ((ignore_mask >> i) & 1))
continue;
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = &srm_irq_type;
+ irq_desc[i].chip = &srm_irq_type;
}
}
if (i >= 16+20 && i <= 16+30)
continue;
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = &alcor_irq_type;
+ irq_desc[i].chip = &alcor_irq_type;
}
i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq;
for (i = 16; i < 35; ++i) {
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = &cabriolet_irq_type;
+ irq_desc[i].chip = &cabriolet_irq_type;
}
}
long i;
for (i = imin; i <= imax; ++i) {
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = ops;
+ irq_desc[i].chip = ops;
}
}
for (i = 16; i < 32; ++i) {
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = &eb64p_irq_type;
+ irq_desc[i].chip = &eb64p_irq_type;
}
common_init_isa_dma();
for (i = 16; i < 128; ++i) {
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = &eiger_irq_type;
+ irq_desc[i].chip = &eiger_irq_type;
}
}
{
init_i8259a_irqs();
- irq_desc[1].handler = &jensen_local_irq_type;
- irq_desc[4].handler = &jensen_local_irq_type;
- irq_desc[3].handler = &jensen_local_irq_type;
- irq_desc[7].handler = &jensen_local_irq_type;
- irq_desc[9].handler = &jensen_local_irq_type;
+ irq_desc[1].chip = &jensen_local_irq_type;
+ irq_desc[4].chip = &jensen_local_irq_type;
+ irq_desc[3].chip = &jensen_local_irq_type;
+ irq_desc[7].chip = &jensen_local_irq_type;
+ irq_desc[9].chip = &jensen_local_irq_type;
common_init_isa_dma();
}
/* Set up the lsi irqs. */
for (i = 0; i < 128; ++i) {
irq_desc[base + i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[base + i].handler = lsi_ops;
+ irq_desc[base + i].chip = lsi_ops;
}
/* Disable the implemented irqs in hardware. */
/* Set up the msi irqs. */
for (i = 128; i < (128 + 512); ++i) {
irq_desc[base + i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[base + i].handler = msi_ops;
+ irq_desc[base + i].chip = msi_ops;
}
for (i = 0; i < 16; ++i)
/* Reserve the legacy irqs. */
for (i = 0; i < 16; ++i) {
irq_desc[i].status = IRQ_DISABLED;
- irq_desc[i].handler = &marvel_legacy_irq_type;
+ irq_desc[i].chip = &marvel_legacy_irq_type;
}
/* Init the io7 irqs. */
for (i = 16; i < 32; ++i) {
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = &mikasa_irq_type;
+ irq_desc[i].chip = &mikasa_irq_type;
}
init_i8259a_irqs();
for (i = 16; i < 48; ++i) {
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = &noritake_irq_type;
+ irq_desc[i].chip = &noritake_irq_type;
}
init_i8259a_irqs();
for (i = 16; i < 128; ++i) {
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = &rawhide_irq_type;
+ irq_desc[i].chip = &rawhide_irq_type;
}
init_i8259a_irqs();
rx164_update_irq_hw(0);
for (i = 16; i < 40; ++i) {
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = &rx164_irq_type;
+ irq_desc[i].chip = &rx164_irq_type;
}
init_i8259a_irqs();
for (i = 0; i < nr_irqs; ++i) {
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = &sable_lynx_irq_type;
+ irq_desc[i].chip = &sable_lynx_irq_type;
}
common_init_isa_dma();
for (i = 16; i < 128; ++i) {
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = &takara_irq_type;
+ irq_desc[i].chip = &takara_irq_type;
}
common_init_isa_dma();
long i;
for (i = imin; i <= imax; ++i) {
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i].handler = ops;
+ irq_desc[i].chip = ops;
}
}
if (i == 2)
continue;
irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i+irq_bias].handler = &wildfire_irq_type;
+ irq_desc[i+irq_bias].chip = &wildfire_irq_type;
}
irq_desc[36+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[36+irq_bias].handler = &wildfire_irq_type;
+ irq_desc[36+irq_bias].chip = &wildfire_irq_type;
for (i = 40; i < 64; ++i) {
irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL;
- irq_desc[i+irq_bias].handler = &wildfire_irq_type;
+ irq_desc[i+irq_bias].chip = &wildfire_irq_type;
}
setup_irq(32+irq_bias, &isa_enable);
/* Initialize IRQ handler descriptiors. */
for(i = 2; i < NR_IRQS; i++) {
- irq_desc[i].handler = &crisv10_irq_type;
+ irq_desc[i].chip = &crisv10_irq_type;
set_int_vector(i, interrupt[i]);
}
/* Point all IRQ's to bad handlers. */
for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
- irq_desc[j].handler = &crisv32_irq_type;
+ irq_desc[j].chip = &crisv32_irq_type;
set_exception_vector(i, interrupt[j]);
}
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#endif
- seq_printf(p, " %14s", irq_desc[i].handler->typename);
+ seq_printf(p, " %14s", irq_desc[i].chip->typename);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
{
disable_irq_nosync(irq);
io_apic_irqs &= ~(1<<irq);
- irq_desc[irq].handler = &i8259A_irq_type;
+ irq_desc[irq].chip = &i8259A_irq_type;
enable_irq(irq);
}
/*
* 16 old-style INTA-cycle interrupts:
*/
- irq_desc[i].handler = &i8259A_irq_type;
+ irq_desc[i].chip = &i8259A_irq_type;
} else {
/*
* 'high' PCI IRQs filled in on demand
*/
- irq_desc[i].handler = &no_irq_type;
+ irq_desc[i].chip = &no_irq_type;
}
}
}
#define IOAPIC_EDGE 0
#define IOAPIC_LEVEL 1
-static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
+static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
{
- unsigned idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
+ unsigned idx;
+
+ idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
trigger == IOAPIC_LEVEL)
- irq_desc[idx].handler = &ioapic_level_type;
+ irq_desc[idx].chip = &ioapic_level_type;
else
- irq_desc[idx].handler = &ioapic_edge_type;
+ irq_desc[idx].chip = &ioapic_edge_type;
set_intr_gate(vector, interrupt[idx]);
}
* The timer IRQ doesn't have to know that behind the
* scene we have a 8259A-master in AEOI mode ...
*/
- irq_desc[0].handler = &ioapic_edge_type;
+ irq_desc[0].chip = &ioapic_edge_type;
/*
* Add it to the IO-APIC irq-routing table:
make_8259A_irq(irq);
else
/* Strange. Oh, well.. */
- irq_desc[irq].handler = &no_irq_type;
+ irq_desc[irq].chip = &no_irq_type;
}
}
}
printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
disable_8259A_irq(0);
- irq_desc[0].handler = &lapic_irq_type;
+ irq_desc[0].chip = &lapic_irq_type;
apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
enable_8259A_irq(0);
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#endif
- seq_printf(p, " %14s", irq_desc[i].handler->typename);
+ seq_printf(p, " %14s", irq_desc[i].chip->typename);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
printk("Breaking affinity for irq %i\n", irq);
mask = map;
}
- if (irq_desc[irq].handler->set_affinity)
- irq_desc[irq].handler->set_affinity(irq, mask);
+ if (irq_desc[irq].chip->set_affinity)
+ irq_desc[irq].chip->set_affinity(irq, mask);
else if (irq_desc[irq].action && !(warned++))
printk("Cannot set affinity for irq %i\n", irq);
}
irq_desc[i].depth = 1;
if (i == 0) {
- irq_desc[i].handler = &cobalt_irq_type;
+ irq_desc[i].chip = &cobalt_irq_type;
}
else if (i == CO_IRQ_IDE0) {
- irq_desc[i].handler = &cobalt_irq_type;
+ irq_desc[i].chip = &cobalt_irq_type;
}
else if (i == CO_IRQ_IDE1) {
- irq_desc[i].handler = &cobalt_irq_type;
+ irq_desc[i].chip = &cobalt_irq_type;
}
else if (i == CO_IRQ_8259) {
- irq_desc[i].handler = &piix4_master_irq_type;
+ irq_desc[i].chip = &piix4_master_irq_type;
}
else if (i < CO_IRQ_APIC0) {
- irq_desc[i].handler = &piix4_virtual_irq_type;
+ irq_desc[i].chip = &piix4_virtual_irq_type;
}
else if (IS_CO_APIC(i)) {
- irq_desc[i].handler = &cobalt_irq_type;
+ irq_desc[i].chip = &cobalt_irq_type;
}
}
* This is for later: first 16 correspond to PC IRQs; next 16
* are Primary MC IRQs and final 16 are Secondary MC IRQs */
for(i = 0; i < 48; i++)
- irq_desc[i].handler = &vic_irq_type;
+ irq_desc[i].chip = &vic_irq_type;
}
/* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
irq_type = &irq_type_iosapic_level;
idesc = irq_descp(vector);
- if (idesc->handler != irq_type) {
- if (idesc->handler != &no_irq_type)
+ if (idesc->chip != irq_type) {
+ if (idesc->chip != &no_irq_type)
printk(KERN_WARNING
"%s: changing vector %d from %s to %s\n",
__FUNCTION__, vector,
- idesc->handler->typename, irq_type->typename);
- idesc->handler = irq_type;
+ idesc->chip->typename, irq_type->typename);
+ idesc->chip = irq_type;
}
return 0;
}
BUG_ON(iosapic_intr_info[vector].count);
/* Clear the interrupt controller descriptor */
- idesc->handler = &no_irq_type;
+ idesc->chip = &no_irq_type;
/* Clear the interrupt information */
memset(&iosapic_intr_info[vector], 0,
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
}
#endif
- seq_printf(p, " %14s", irq_desc[i].handler->typename);
+ seq_printf(p, " %14s", irq_desc[i].chip->typename);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
/*
* Al three are essential, currently WARN_ON.. maybe panic?
*/
- if (desc->handler && desc->handler->disable &&
- desc->handler->enable && desc->handler->set_affinity) {
- desc->handler->disable(irq);
- desc->handler->set_affinity(irq, mask);
- desc->handler->enable(irq);
+ if (desc->chip && desc->chip->disable &&
+ desc->chip->enable && desc->chip->set_affinity) {
+ desc->chip->disable(irq);
+ desc->chip->set_affinity(irq, mask);
+ desc->chip->enable(irq);
} else {
- WARN_ON((!(desc->handler) || !(desc->handler->disable) ||
- !(desc->handler->enable) ||
- !(desc->handler->set_affinity)));
+ WARN_ON((!(desc->chip) || !(desc->chip->disable) ||
+ !(desc->chip->enable) ||
+ !(desc->chip->set_affinity)));
}
}
}
if (irq_to_vector(irq) == vec) {
desc = irq_descp(irq);
desc->status |= IRQ_PER_CPU;
- desc->handler = &irq_type_ia64_lsapic;
+ desc->chip = &irq_type_ia64_lsapic;
if (action)
setup_irq(irq, action);
}
* polling before making changes.
*/
if (desc) {
- desc->handler->disable(ia64_cpe_irq);
- desc->handler->set_affinity(ia64_cpe_irq, mask);
- desc->handler->enable(ia64_cpe_irq);
+ desc->chip->disable(ia64_cpe_irq);
+ desc->chip->set_affinity(ia64_cpe_irq, mask);
+ desc->chip->enable(ia64_cpe_irq);
printk ("Re-targetting CPEI to cpu %d\n", new_cpei_cpu);
}
}
ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;
for (i = 0; i < NR_IRQS; i++) {
- if (base_desc[i].handler == &no_irq_type) {
- base_desc[i].handler = &irq_type_sn;
+ if (base_desc[i].chip == &no_irq_type) {
+ base_desc[i].chip = &irq_type_sn;
}
}
}
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#endif
- seq_printf(p, " %14s", irq_desc[i].handler->typename);
+ seq_printf(p, " %14s", irq_desc[i].chip->typename);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
#if defined(CONFIG_SMC91X)
/* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_INT0].handler = &m32104ut_irq_type;
+ irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type;
irq_desc[M32R_IRQ_INT0].action = 0;
irq_desc[M32R_IRQ_INT0].depth = 1;
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */
/* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_MFT2].handler = &m32104ut_irq_type;
+ irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type;
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
#ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_R].handler = &m32104ut_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type;
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
/* SIO0_S : uart send data */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_S].handler = &m32104ut_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type;
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
#if defined(CONFIG_SMC91X)
/* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
- irq_desc[M32700UT_LAN_IRQ_LAN].handler = &m32700ut_lanpld_irq_type;
+ irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type;
irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
/* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_MFT2].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
/* SIO0 : receive */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_R].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
/* SIO0 : send */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_S].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
/* SIO1 : receive */
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_R].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_SIO1_R].action = 0;
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
/* SIO1 : send */
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_S].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_SIO1_S].action = 0;
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
/* DMA1 : */
irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_DMA1].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_DMA1].action = 0;
irq_desc[M32R_IRQ_DMA1].depth = 1;
icu_data[M32R_IRQ_DMA1].icucr = 0;
#ifdef CONFIG_SERIAL_M32R_PLDSIO
/* INT#1: SIO0 Receive on PLD */
irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_SIO0_RCV].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
/* INT#1: SIO0 Send on PLD */
irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_SIO0_SND].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_SIO0_SND].action = 0;
irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
/* INT#1: CFC IREQ on PLD */
irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_CFIREQ].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_CFIREQ].action = 0;
irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
/* INT#1: CFC Insert on PLD */
irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_CFC_INSERT].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
/* INT#1: CFC Eject on PLD */
irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_CFC_EJECT].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
- irq_desc[M32700UT_LCD_IRQ_USB_INT1].handler = &m32700ut_lcdpld_irq_type;
+ irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type;
irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
* INT3# is used for AR
*/
irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_INT3].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_INT3].action = 0;
irq_desc[M32R_IRQ_INT3].depth = 1;
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
#ifdef CONFIG_NE2000
/* INT0 : LAN controller (RTL8019AS) */
irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_INT0].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type;
irq_desc[M32R_IRQ_INT0].action = 0;
irq_desc[M32R_IRQ_INT0].depth = 1;
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
/* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_MFT2].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
#ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_R].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
/* SIO0_S : uart send data */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_S].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
/* SIO1_R : uart receive data */
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_R].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;
irq_desc[M32R_IRQ_SIO1_R].action = 0;
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
/* SIO1_S : uart send data */
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_S].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;
irq_desc[M32R_IRQ_SIO1_S].action = 0;
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
#if defined(CONFIG_M32R_PCC)
/* INT1 : pccard0 interrupt */
irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_INT1].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type;
irq_desc[M32R_IRQ_INT1].action = 0;
irq_desc[M32R_IRQ_INT1].depth = 1;
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
/* INT2 : pccard1 interrupt */
irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_INT2].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type;
irq_desc[M32R_IRQ_INT2].action = 0;
irq_desc[M32R_IRQ_INT2].depth = 1;
icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
#if defined(CONFIG_SMC91X)
/* INT0 : LAN controller (SMC91111) */
irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_INT0].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_INT0].chip = &mappi2_irq_type;
irq_desc[M32R_IRQ_INT0].action = 0;
irq_desc[M32R_IRQ_INT0].depth = 1;
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
/* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_MFT2].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_MFT2].chip = &mappi2_irq_type;
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
#ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_R].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].chip = &mappi2_irq_type;
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
/* SIO0_S : uart send data */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_S].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].chip = &mappi2_irq_type;
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
disable_mappi2_irq(M32R_IRQ_SIO0_S);
/* SIO1_R : uart receive data */
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_R].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_SIO1_R].chip = &mappi2_irq_type;
irq_desc[M32R_IRQ_SIO1_R].action = 0;
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
/* SIO1_S : uart send data */
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_S].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_SIO1_S].chip = &mappi2_irq_type;
irq_desc[M32R_IRQ_SIO1_S].action = 0;
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
#if defined(CONFIG_USB)
/* INT1 : USB Host controller interrupt */
irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_INT1].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type;
irq_desc[M32R_IRQ_INT1].action = 0;
irq_desc[M32R_IRQ_INT1].depth = 1;
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
/* ICUCR40: CFC IREQ */
irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_CFIREQ].handler = &mappi2_irq_type;
+ irq_desc[PLD_IRQ_CFIREQ].chip = &mappi2_irq_type;
irq_desc[PLD_IRQ_CFIREQ].action = 0;
irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
#if defined(CONFIG_M32R_CFC)
/* ICUCR41: CFC Insert */
irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_CFC_INSERT].handler = &mappi2_irq_type;
+ irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi2_irq_type;
irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
/* ICUCR42: CFC Eject */
irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_CFC_EJECT].handler = &mappi2_irq_type;
+ irq_desc[PLD_IRQ_CFC_EJECT].chip = &mappi2_irq_type;
irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
#if defined(CONFIG_SMC91X)
/* INT0 : LAN controller (SMC91111) */
irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_INT0].handler = &mappi3_irq_type;
+ irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type;
irq_desc[M32R_IRQ_INT0].action = 0;
irq_desc[M32R_IRQ_INT0].depth = 1;
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
/* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_MFT2].handler = &mappi3_irq_type;
+ irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type;
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
#ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_R].handler = &mappi3_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type;
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
/* SIO0_S : uart send data */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_S].handler = &mappi3_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type;
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
disable_mappi3_irq(M32R_IRQ_SIO0_S);
/* SIO1_R : uart receive data */
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_R].handler = &mappi3_irq_type;
+ irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type;
irq_desc[M32R_IRQ_SIO1_R].action = 0;
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
/* SIO1_S : uart send data */
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_S].handler = &mappi3_irq_type;
+ irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type;
irq_desc[M32R_IRQ_SIO1_S].action = 0;
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
#if defined(CONFIG_USB)
/* INT1 : USB Host controller interrupt */
irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_INT1].handler = &mappi3_irq_type;
+ irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type;
irq_desc[M32R_IRQ_INT1].action = 0;
irq_desc[M32R_IRQ_INT1].depth = 1;
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
/* CFC IREQ */
irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_CFIREQ].handler = &mappi3_irq_type;
+ irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type;
irq_desc[PLD_IRQ_CFIREQ].action = 0;
irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
#if defined(CONFIG_M32R_CFC)
/* ICUCR41: CFC Insert & eject */
irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_CFC_INSERT].handler = &mappi3_irq_type;
+ irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type;
irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
/* IDE IREQ */
irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_IDEIREQ].handler = &mappi3_irq_type;
+ irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type;
irq_desc[PLD_IRQ_IDEIREQ].action = 0;
irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */
icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
#ifdef CONFIG_NE2000
/* INT3 : LAN controller (RTL8019AS) */
irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_INT3].handler = &oaks32r_irq_type;
+ irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type;
irq_desc[M32R_IRQ_INT3].action = 0;
irq_desc[M32R_IRQ_INT3].depth = 1;
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
/* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_MFT2].handler = &oaks32r_irq_type;
+ irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type;
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
#ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_R].handler = &oaks32r_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type;
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
/* SIO0_S : uart send data */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_S].handler = &oaks32r_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type;
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
/* SIO1_R : uart receive data */
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_R].handler = &oaks32r_irq_type;
+ irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type;
irq_desc[M32R_IRQ_SIO1_R].action = 0;
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
/* SIO1_S : uart send data */
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_S].handler = &oaks32r_irq_type;
+ irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type;
irq_desc[M32R_IRQ_SIO1_S].action = 0;
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
#if defined(CONFIG_SMC91X)
/* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED;
- irq_desc[OPSPUT_LAN_IRQ_LAN].handler = &opsput_lanpld_irq_type;
+ irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type;
irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
/* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_MFT2].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type;
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
/* SIO0 : receive */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_R].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type;
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
/* SIO0 : send */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_S].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type;
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
/* SIO1 : receive */
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_R].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type;
irq_desc[M32R_IRQ_SIO1_R].action = 0;
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
/* SIO1 : send */
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_S].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type;
irq_desc[M32R_IRQ_SIO1_S].action = 0;
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
/* DMA1 : */
irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_DMA1].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type;
irq_desc[M32R_IRQ_DMA1].action = 0;
irq_desc[M32R_IRQ_DMA1].depth = 1;
icu_data[M32R_IRQ_DMA1].icucr = 0;
#ifdef CONFIG_SERIAL_M32R_PLDSIO
/* INT#1: SIO0 Receive on PLD */
irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_SIO0_RCV].handler = &opsput_pld_irq_type;
+ irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type;
irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
/* INT#1: SIO0 Send on PLD */
irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_SIO0_SND].handler = &opsput_pld_irq_type;
+ irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type;
irq_desc[PLD_IRQ_SIO0_SND].action = 0;
irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
#if defined(CONFIG_M32R_CFC)
/* INT#1: CFC IREQ on PLD */
irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_CFIREQ].handler = &opsput_pld_irq_type;
+ irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type;
irq_desc[PLD_IRQ_CFIREQ].action = 0;
irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
/* INT#1: CFC Insert on PLD */
irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_CFC_INSERT].handler = &opsput_pld_irq_type;
+ irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type;
irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
/* INT#1: CFC Eject on PLD */
irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_CFC_EJECT].handler = &opsput_pld_irq_type;
+ irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type;
irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
- irq_desc[OPSPUT_LCD_IRQ_USB_INT1].handler = &opsput_lcdpld_irq_type;
+ irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type;
irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0;
irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
* INT3# is used for AR
*/
irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_INT3].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type;
irq_desc[M32R_IRQ_INT3].action = 0;
irq_desc[M32R_IRQ_INT3].depth = 1;
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
/* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_MFT2].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
#if defined(CONFIG_SERIAL_M32R_SIO)
/* SIO0_R : uart receive data */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_R].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
/* SIO0_S : uart send data */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO0_S].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
/* SIO1_R : uart receive data */
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_R].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;
irq_desc[M32R_IRQ_SIO1_R].action = 0;
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
/* SIO1_S : uart send data */
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
- irq_desc[M32R_IRQ_SIO1_S].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;
irq_desc[M32R_IRQ_SIO1_S].action = 0;
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
/* INT#67-#71: CFC#0 IREQ on PLD */
for (i = 0 ; i < CONFIG_CFC_NUM ; i++ ) {
irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_CF0 + i].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_CF0 + i].action = 0;
irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
/* INT#76: 16552D#0 IREQ on PLD */
irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_UART0].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_UART0].action = 0;
irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
/* INT#77: 16552D#1 IREQ on PLD */
irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_UART1].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_UART1].action = 0;
irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
/* INT#80: AK4524 IREQ on PLD */
irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED;
- irq_desc[PLD_IRQ_SNDINT].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_SNDINT].action = 0;
irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
au_writel(1<<(irq_nr-32), IC1_CFG0SET);
- irq_desc[irq_nr].handler = &rise_edge_irq_type;
+ irq_desc[irq_nr].chip = &rise_edge_irq_type;
break;
case INTC_INT_FALL_EDGE: /* 0:1:0 */
au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
au_writel(1<<(irq_nr-32), IC1_CFG1SET);
au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
- irq_desc[irq_nr].handler = &fall_edge_irq_type;
+ irq_desc[irq_nr].chip = &fall_edge_irq_type;
break;
case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
au_writel(1<<(irq_nr-32), IC1_CFG1SET);
au_writel(1<<(irq_nr-32), IC1_CFG0SET);
- irq_desc[irq_nr].handler = &either_edge_irq_type;
+ irq_desc[irq_nr].chip = &either_edge_irq_type;
break;
case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
au_writel(1<<(irq_nr-32), IC1_CFG2SET);
au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
au_writel(1<<(irq_nr-32), IC1_CFG0SET);
- irq_desc[irq_nr].handler = &level_irq_type;
+ irq_desc[irq_nr].chip = &level_irq_type;
break;
case INTC_INT_LOW_LEVEL: /* 1:1:0 */
au_writel(1<<(irq_nr-32), IC1_CFG2SET);
au_writel(1<<(irq_nr-32), IC1_CFG1SET);
au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
- irq_desc[irq_nr].handler = &level_irq_type;
+ irq_desc[irq_nr].chip = &level_irq_type;
break;
case INTC_INT_DISABLED: /* 0:0:0 */
au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
au_writel(1<<irq_nr, IC0_CFG2CLR);
au_writel(1<<irq_nr, IC0_CFG1CLR);
au_writel(1<<irq_nr, IC0_CFG0SET);
- irq_desc[irq_nr].handler = &rise_edge_irq_type;
+ irq_desc[irq_nr].chip = &rise_edge_irq_type;
break;
case INTC_INT_FALL_EDGE: /* 0:1:0 */
au_writel(1<<irq_nr, IC0_CFG2CLR);
au_writel(1<<irq_nr, IC0_CFG1SET);
au_writel(1<<irq_nr, IC0_CFG0CLR);
- irq_desc[irq_nr].handler = &fall_edge_irq_type;
+ irq_desc[irq_nr].chip = &fall_edge_irq_type;
break;
case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
au_writel(1<<irq_nr, IC0_CFG2CLR);
au_writel(1<<irq_nr, IC0_CFG1SET);
au_writel(1<<irq_nr, IC0_CFG0SET);
- irq_desc[irq_nr].handler = &either_edge_irq_type;
+ irq_desc[irq_nr].chip = &either_edge_irq_type;
break;
case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
au_writel(1<<irq_nr, IC0_CFG2SET);
au_writel(1<<irq_nr, IC0_CFG1CLR);
au_writel(1<<irq_nr, IC0_CFG0SET);
- irq_desc[irq_nr].handler = &level_irq_type;
+ irq_desc[irq_nr].chip = &level_irq_type;
break;
case INTC_INT_LOW_LEVEL: /* 1:1:0 */
au_writel(1<<irq_nr, IC0_CFG2SET);
au_writel(1<<irq_nr, IC0_CFG1SET);
au_writel(1<<irq_nr, IC0_CFG0CLR);
- irq_desc[irq_nr].handler = &level_irq_type;
+ irq_desc[irq_nr].chip = &level_irq_type;
break;
case INTC_INT_DISABLED: /* 0:0:0 */
au_writel(1<<irq_nr, IC0_CFG0CLR);
for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++)
{
- irq_desc[irq_nr].handler = &external_irq_type;
+ irq_desc[irq_nr].chip = &external_irq_type;
pb1200_disable_irq(irq_nr);
}
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &vrc5477_irq_controller;
+ irq_desc[i].chip = &vrc5477_irq_controller;
}
vrc5477_irq_base = irq_base;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &ioasic_irq_type;
+ irq_desc[i].chip = &ioasic_irq_type;
}
for (; i < base + IO_IRQ_LINES; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &ioasic_dma_irq_type;
+ irq_desc[i].chip = &ioasic_dma_irq_type;
}
ioasic_irq_base = base;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &kn02_irq_type;
+ irq_desc[i].chip = &kn02_irq_type;
}
kn02_irq_base = base;
/* Let's initialize our IRQ descriptors */
for (i = 0; i < NR_IRQS; i++) {
irq_desc[i].status = 0;
- irq_desc[i].handler = &no_irq_type;
+ irq_desc[i].chip = &no_irq_type;
irq_desc[i].action = NULL;
irq_desc[i].depth = 0;
spin_lock_init(&irq_desc[i].lock);
#endif
for (i = 0; i <= IT8172_LAST_IRQ; i++) {
- irq_desc[i].handler = &it8172_irq_type;
+ irq_desc[i].chip = &it8172_irq_type;
spin_lock_init(&irq_desc[i].lock);
}
- irq_desc[MIPS_CPU_TIMER_IRQ].handler = &cp0_irq_type;
+ irq_desc[MIPS_CPU_TIMER_IRQ].chip = &cp0_irq_type;
set_c0_status(ALLINTS_NOTIMER);
}
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &r4030_irq_type;
+ irq_desc[i].chip = &r4030_irq_type;
}
r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &jmr3927_irq_controller;
+ irq_desc[i].chip = &jmr3927_irq_controller;
}
jmr3927_irq_base = irq_base;
void make_8259A_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- irq_desc[irq].handler = &i8259A_irq_type;
+ irq_desc[irq].chip = &i8259A_irq_type;
enable_irq(irq);
}
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &i8259A_irq_type;
+ irq_desc[i].chip = &i8259A_irq_type;
}
setup_irq(2, &irq2);
switch (imp->im_type) {
case MSC01_IRQ_EDGE:
- irq_desc[base+n].handler = &msc_edgeirq_type;
+ irq_desc[base+n].chip = &msc_edgeirq_type;
if (cpu_has_veic)
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
else
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
break;
case MSC01_IRQ_LEVEL:
- irq_desc[base+n].handler = &msc_levelirq_type;
+ irq_desc[base+n].chip = &msc_levelirq_type;
if (cpu_has_veic)
MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
else
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 2;
- irq_desc[i].handler = &mv64340_irq_type;
+ irq_desc[i].chip = &mv64340_irq_type;
}
irq_base = base;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &rm7k_irq_controller;
+ irq_desc[i].chip = &rm7k_irq_controller;
}
irq_base = base;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &rm9k_irq_controller;
+ irq_desc[i].chip = &rm9k_irq_controller;
}
rm9000_perfcount_irq = base + 1;
- irq_desc[rm9000_perfcount_irq].handler = &rm9k_perfcounter_irq;
+ irq_desc[rm9000_perfcount_irq].chip = &rm9k_perfcounter_irq;
irq_base = base;
}
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#endif
- seq_printf(p, " %14s", irq_desc[i].handler->typename);
+ seq_printf(p, " %14s", irq_desc[i].chip->typename);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &no_irq_type;
+ irq_desc[i].chip = &no_irq_type;
spin_lock_init(&irq_desc[i].lock);
#ifdef CONFIG_MIPS_MT_SMTC
irq_hwmask[i] = 0;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &mips_mt_cpu_irq_controller;
+ irq_desc[i].chip = &mips_mt_cpu_irq_controller;
}
for (i = irq_base + 2; i < irq_base + 8; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &mips_cpu_irq_controller;
+ irq_desc[i].chip = &mips_cpu_irq_controller;
}
mips_cpu_irq_base = irq_base;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &lasat_irq_type;
+ irq_desc[i].chip = &lasat_irq_type;
}
}
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &atlas_irq_type;
+ irq_desc[i].chip = &atlas_irq_type;
spin_lock_init(&irq_desc[i].lock);
}
}
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 2;
- irq_desc[i].handler = &cpci_irq_type;
+ irq_desc[i].chip = &cpci_irq_type;
}
}
irq_desc[80].status = IRQ_DISABLED;
irq_desc[80].action = 0;
irq_desc[80].depth = 2;
- irq_desc[80].handler = &uart_irq_type;
+ irq_desc[80].chip = &uart_irq_type;
irq_desc[81].status = IRQ_DISABLED;
irq_desc[81].action = 0;
irq_desc[81].depth = 2;
- irq_desc[81].handler = &uart_irq_type;
+ irq_desc[81].chip = &uart_irq_type;
}
int configPR;
for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
- irq_desc[i].handler = &level_irq_type;
+ irq_desc[i].chip = &level_irq_type;
pnx8550_ack(i); /* mask the irq just in case */
}
/* mask/priority is still 0 so we will not get any
* interrupts until it is unmasked */
- irq_desc[i].handler = &level_irq_type;
+ irq_desc[i].chip = &level_irq_type;
}
/* Priority level 0 */
/* Set int vector table address */
PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
- irq_desc[MIPS_CPU_GIC_IRQ].handler = &level_irq_type;
+ irq_desc[MIPS_CPU_GIC_IRQ].chip = &level_irq_type;
setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
/* init of Timer interrupts */
for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) {
- irq_desc[i].handler = &level_irq_type;
+ irq_desc[i].chip = &level_irq_type;
}
/* Stop Timer 1-3 */
configPR |= 0x00000038;
write_c0_config7(configPR);
- irq_desc[MIPS_CPU_TIMER_IRQ].handler = &level_irq_type;
+ irq_desc[MIPS_CPU_TIMER_IRQ].chip = &level_irq_type;
setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
}
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
if (i < (SGINT_EISA + 8))
- irq_desc[i].handler = &ip22_eisa1_irq_type;
+ irq_desc[i].chip = &ip22_eisa1_irq_type;
else
- irq_desc[i].handler = &ip22_eisa2_irq_type;
+ irq_desc[i].chip = &ip22_eisa2_irq_type;
}
/* Cannot use request_irq because of kmalloc not being ready at such
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
- irq_desc[i].handler = handler;
+ irq_desc[i].chip = handler;
}
/* vector handler. this register the IRQ as non-sharable */
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
- irq_desc[irq].handler = &bridge_irq_type;
+ irq_desc[irq].chip = &bridge_irq_type;
}
int __devinit request_bridge_irq(struct bridge_controller *bc)
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 0;
- irq_desc[irq].handler = controller;
+ irq_desc[irq].chip = controller;
}
setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
if (i < BCM1480_NR_IRQS) {
- irq_desc[i].handler = &bcm1480_irq_type;
+ irq_desc[i].chip = &bcm1480_irq_type;
bcm1480_irq_owner[i] = 0;
} else {
- irq_desc[i].handler = &no_irq_type;
+ irq_desc[i].chip = &no_irq_type;
}
}
}
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
if (i < SB1250_NR_IRQS) {
- irq_desc[i].handler = &sb1250_irq_type;
+ irq_desc[i].chip = &sb1250_irq_type;
sb1250_irq_owner[i] = 0;
} else {
- irq_desc[i].handler = &no_irq_type;
+ irq_desc[i].chip = &no_irq_type;
}
}
}
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &pciasic_irq_type;
+ irq_desc[i].chip = &pciasic_irq_type;
}
change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &tx4927_irq_cp0_type;
+ irq_desc[i].chip = &tx4927_irq_cp0_type;
}
return;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 2;
- irq_desc[i].handler = &tx4927_irq_pic_type;
+ irq_desc[i].chip = &tx4927_irq_pic_type;
}
setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action);
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 3;
- irq_desc[i].handler = &toshiba_rbtx4927_irq_ioc_type;
+ irq_desc[i].chip = &toshiba_rbtx4927_irq_ioc_type;
}
setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
irq_desc[i].action = 0;
irq_desc[i].depth =
((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5));
- irq_desc[i].handler = &toshiba_rbtx4927_irq_isa_type;
+ irq_desc[i].chip = &toshiba_rbtx4927_irq_isa_type;
}
setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
{
u32 i, j = 0;
for (i = 0; i < NR_IRQS; i++) {
- if (strcmp(irq_desc[i].handler->typename, "none")
+ if (strcmp(irq_desc[i].chip->typename, "none")
== 0)
continue;
if ((i >= 1)
- && (irq_desc[i - 1].handler->typename ==
- irq_desc[i].handler->typename)) {
+ && (irq_desc[i - 1].chip->typename ==
+ irq_desc[i].chip->typename)) {
j++;
} else {
j = 0;
(TOSHIBA_RBTX4927_IRQ_INFO,
"%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n",
key, i, i, irq_desc[i].status,
- (u32) irq_desc[i].handler,
+ (u32) irq_desc[i].chip,
(u32) irq_desc[i].action,
(u32) (irq_desc[i].action ? irq_desc[i].
action->handler : 0),
irq_desc[i].depth,
- irq_desc[i].handler->typename, j);
+ irq_desc[i].chip->typename, j);
}
}
#endif
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &tx4938_irq_cp0_type;
+ irq_desc[i].chip = &tx4938_irq_cp0_type;
}
return;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 2;
- irq_desc[i].handler = &tx4938_irq_pic_type;
+ irq_desc[i].chip = &tx4938_irq_pic_type;
}
setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 3;
- irq_desc[i].handler = &toshiba_rbtx4938_irq_ioc_type;
+ irq_desc[i].chip = &toshiba_rbtx4938_irq_ioc_type;
}
setup_irq(RBTX4938_IRQ_IOCINT,
icu2_write(MGIUINTHREG, 0xffff);
for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
- irq_desc[i].handler = &sysint1_irq_type;
+ irq_desc[i].chip = &sysint1_irq_type;
for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
- irq_desc[i].handler = &sysint2_irq_type;
+ irq_desc[i].chip = &sysint2_irq_type;
cascade_irq(INT0_IRQ, icu_get_irq);
cascade_irq(INT1_IRQ, icu_get_irq);
if (cascade->get_irq != NULL) {
unsigned int source_irq = irq;
desc = irq_desc + source_irq;
- desc->handler->ack(source_irq);
+ desc->chip->ack(source_irq);
irq = cascade->get_irq(irq, regs);
if (irq < 0)
atomic_inc(&irq_err_count);
else
irq_dispatch(irq, regs);
- desc->handler->end(source_irq);
+ desc->chip->end(source_irq);
} else
do_IRQ(irq, regs);
}
vr41xx_set_irq_level(GIU_IRQ_TO_PIN(cascade_irq), LEVEL_LOW);
for (i = VRC4173_IRQ_BASE; i <= VRC4173_IRQ_LAST; i++)
- irq_desc[i].handler = &vrc4173_irq_type;
+ irq_desc[i].chip = &vrc4173_irq_type;
return 0;
}
}
for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++)
- irq_desc[i].handler = &i8259_irq_type;
+ irq_desc[i].chip = &i8259_irq_type;
setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade);
seq_printf(p, "%10u ", kstat_irqs(i));
#endif
- seq_printf(p, " %14s", irq_desc[i].handler->typename);
+ seq_printf(p, " %14s", irq_desc[i].chip->typename);
#ifndef PARISC_IRQ_CR16_COUNTS
seq_printf(p, " %s", action->name);
{
if (irq_desc[irq].action)
return -EBUSY;
- if (irq_desc[irq].handler != &cpu_interrupt_type)
+ if (irq_desc[irq].chip != &cpu_interrupt_type)
return -EBUSY;
if (type) {
- irq_desc[irq].handler = type;
- irq_desc[irq].handler_data = data;
+ irq_desc[irq].chip = type;
+ irq_desc[irq].chip_data = data;
cpu_interrupt_type.enable(irq);
}
return 0;
{
int i;
for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
- irq_desc[i].handler = &cpu_interrupt_type;
+ irq_desc[i].chip = &cpu_interrupt_type;
}
irq_desc[TIMER_IRQ].action = &timer_action;
struct irq_desc *desc = irq_descp(irq);
if (desc->status & IRQ_INPROGRESS)
- desc->handler->end(irq);
+ desc->chip->end(irq);
if (!(desc->status & IRQ_DISABLED))
- desc->handler->disable(irq);
+ desc->chip->disable(irq);
}
if (ppc_md.kexec_cpu_down)
#else
seq_printf(p, "%10u ", kstat_irqs(i));
#endif /* CONFIG_SMP */
- if (desc->handler)
- seq_printf(p, " %s ", desc->handler->typename);
+ if (desc->chip)
+ seq_printf(p, " %s ", desc->chip->typename);
else
seq_puts(p, " None ");
seq_printf(p, "%s", (desc->status & IRQ_LEVEL) ? "Level " : "Edge ");
printk("Breaking affinity for irq %i\n", irq);
mask = map;
}
- if (irq_desc[irq].handler->set_affinity)
- irq_desc[irq].handler->set_affinity(irq, mask);
+ if (irq_desc[irq].chip->set_affinity)
+ irq_desc[irq].chip->set_affinity(irq, mask);
else if (irq_desc[irq].action && !(warned++))
printk("Cannot set affinity for irq %i\n", irq);
}
irq = iic_ipi_to_irq(ipi);
/* IPIs are marked SA_INTERRUPT as they must run with irqs
* disabled */
- get_irq_desc(irq)->handler = &iic_pic;
+ get_irq_desc(irq)->chip = &iic_pic;
get_irq_desc(irq)->status |= IRQ_PER_CPU;
request_irq(irq, iic_ipi_action, SA_INTERRUPT, name, NULL);
}
for (be=0; be < num_present_cpus() / 2; be++) {
for (isrc = 0; isrc < IIC_CLASS_STRIDE * 3; isrc++) {
int irq = IIC_NODE_STRIDE * be + IIC_SPE_OFFSET + isrc;
- get_irq_desc(irq)->handler = &iic_pic;
+ get_irq_desc(irq)->chip = &iic_pic;
}
}
}
spider_pics[node] = ioremap(spiderpic, 0x800);
for (n = 0; n < IIC_NUM_EXT; n++) {
int irq = n + IIC_EXT_OFFSET + node * IIC_NODE_STRIDE;
- get_irq_desc(irq)->handler = &spider_pic;
+ get_irq_desc(irq)->chip = &spider_pic;
}
/* do not mask any interrupts because of level */
for (n = 0; n < IIC_NUM_EXT; n++) {
int irq = n + IIC_EXT_OFFSET + node * IIC_NODE_STRIDE;
- get_irq_desc(irq)->handler = &spider_pic;
+ get_irq_desc(irq)->chip = &spider_pic;
}
/* do not mask any interrupts because of level */
for_each_irq (irq) {
irq_desc_t *desc = get_irq_desc(irq);
- if (desc && desc->handler && desc->handler->startup) {
+ if (desc && desc->chip && desc->chip->startup) {
spin_lock_irqsave(&desc->lock, flags);
- desc->handler->startup(irq);
+ desc->chip->startup(irq);
spin_unlock_irqrestore(&desc->lock, flags);
}
}
+ function;
virtirq = virt_irq_create_mapping(realirq);
- irq_desc[virtirq].handler = &iSeries_IRQ_handler;
+ irq_desc[virtirq].chip = &iSeries_IRQ_handler;
return virtirq;
}
/* Set the handler for the main PIC */
for ( i = 0; i < max_real_irqs ; i++ )
- irq_desc[i].handler = &pmac_pic;
+ irq_desc[i].chip = &pmac_pic;
/* Get addresses of first controller if we have a node for it */
BUG_ON(of_address_to_resource(master, 0, &r));
/* Setup handlers for secondary controller and hook cascade irq*/
if (slave) {
for ( i = max_real_irqs ; i < max_irqs ; i++ )
- irq_desc[i].handler = &gatwick_pic;
+ irq_desc[i].chip = &gatwick_pic;
setup_irq(irq_cascade, &gatwick_cascade_action);
}
printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
}
for (i = irq_offset_value(); i < NR_IRQS; ++i)
- get_irq_desc(i)->handler = &xics_pic;
+ get_irq_desc(i)->chip = &xics_pic;
xics_setup_cpu();
continue;
/* We only need to migrate enabled IRQS */
- if (desc == NULL || desc->handler == NULL
+ if (desc == NULL || desc->chip == NULL
|| desc->action == NULL
- || desc->handler->set_affinity == NULL)
+ || desc->chip->set_affinity == NULL)
continue;
spin_lock_irqsave(&desc->lock, flags);
virq, cpu);
/* Reset affinity to all cpus */
- desc->handler->set_affinity(virq, CPU_MASK_ALL);
+ desc->chip->set_affinity(virq, CPU_MASK_ALL);
irq_affinity[virq] = CPU_MASK_ALL;
unlock:
spin_unlock_irqrestore(&desc->lock, flags);
spin_unlock_irqrestore(&i8259_lock, flags);
for (i = 0; i < NUM_ISA_INTERRUPTS; ++i)
- irq_desc[offset + i].handler = &i8259_pic;
+ irq_desc[offset + i].chip = &i8259_pic;
/* reserve our resources */
setup_irq(offset + 2, &i8259_irqaction);
ipic_write(primary_ipic->regs, IPIC_SEMSR, temp);
for (i = 0 ; i < NR_IPIC_INTS ; i++) {
- irq_desc[i+irq_offset].handler = &ipic;
+ irq_desc[i+irq_offset].chip = &ipic;
irq_desc[i+irq_offset].status = IRQ_LEVEL;
}
/* Get the mpic structure from the IPI number */
static inline struct mpic * mpic_from_ipi(unsigned int ipi)
{
- return container_of(irq_desc[ipi].handler, struct mpic, hc_ipi);
+ return container_of(irq_desc[ipi].chip, struct mpic, hc_ipi);
}
#endif
/* Get the mpic structure from the irq number */
static inline struct mpic * mpic_from_irq(unsigned int irq)
{
- return container_of(irq_desc[irq].handler, struct mpic, hc_irq);
+ return container_of(irq_desc[irq].chip, struct mpic, hc_irq);
}
/* Send an EOI */
if (!(mpic->flags & MPIC_PRIMARY))
continue;
irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU;
- irq_desc[mpic->ipi_offset+i].handler = &mpic->hc_ipi;
+ irq_desc[mpic->ipi_offset+i].chip = &mpic->hc_ipi;
#endif /* CONFIG_SMP */
}
/* init linux descriptors */
if (i < mpic->irq_count) {
irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0;
- irq_desc[mpic->irq_offset+i].handler = &mpic->hc_irq;
+ irq_desc[mpic->irq_offset+i].chip = &mpic->hc_irq;
}
}
* interrupt vectors
*/
for ( i = CPM_IRQ_OFFSET ; i < CPM_IRQ_OFFSET + NR_CPM_INTS ; i++ )
- irq_desc[i].handler = &cpm_pic;
+ irq_desc[i].chip = &cpm_pic;
/* Set our interrupt handler with the core CPU. */
if (setup_irq(CPM_INTERRUPT, &cpm_interrupt_irqaction))
for ( i = 0 ; i < AMI_IRQS; i++ ) {
irq_desc[i].status = IRQ_LEVEL;
if (i < IRQ_AMIGA_AUTO) {
- irq_desc[i].handler = &amiga_irqctrl;
+ irq_desc[i].chip = &amiga_irqctrl;
} else {
- irq_desc[i].handler = &amiga_sys_irqctrl;
+ irq_desc[i].chip = &amiga_sys_irqctrl;
action = &amiga_sys_irqaction[i-IRQ_AMIGA_AUTO];
if (action->name)
setup_irq(i, action);
/* Set up the interrupt handlers for the i8259 IRQs */
for (i = NR_SIU_INTS; i < NR_SIU_INTS + 8; i++) {
- irq_desc[i].handler = &sbc82xx_i8259_ic;
+ irq_desc[i].chip = &sbc82xx_i8259_ic;
irq_desc[i].status |= IRQ_LEVEL;
}
/* IRQ 0 is highest */
for (i = 0; i < 17; i++) {
- irq_desc[i].handler = &cpc700_pic;
+ irq_desc[i].chip = &cpc700_pic;
cpc700_pic_init_irq(i);
}
for (i = 20; i < 32; i++) {
- irq_desc[i].handler = &cpc700_pic;
+ irq_desc[i].chip = &cpc700_pic;
cpc700_pic_init_irq(i);
}
/* Enable chaining to OpenPIC, and make everything level
*/
for (i = 0; i < NR_CPM_INTS; i++) {
- irq_desc[i+CPM_IRQ_OFFSET].handler = &cpm2_pic;
+ irq_desc[i+CPM_IRQ_OFFSET].chip = &cpm2_pic;
irq_desc[i+CPM_IRQ_OFFSET].status |= IRQ_LEVEL;
}
}
/* use the gt64260 for all (possible) interrupt sources */
for (i = gt64260_irq_base; i < (gt64260_irq_base + 96); i++)
- irq_desc[i].handler = >64260_pic;
+ irq_desc[i].chip = >64260_pic;
if (ppc_md.progress)
ppc_md.progress("gt64260_init_irq: exit", 0x0);
immap->im_memctl.memc_or8 = 0xffff8010;
#endif
for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++)
- irq_desc[irq].handler = &pq2pci_ic;
+ irq_desc[irq].chip = &pq2pci_ic;
/* make PCI IRQ level sensitive */
immap->im_intctl.ic_siexr &=
int i;
for (i = SIU_IRQ_OFFSET ; i < SIU_IRQ_OFFSET + NR_SIU_INTS ; i++)
- irq_desc[i].handler = &ppc8xx_pic;
+ irq_desc[i].chip = &ppc8xx_pic;
cpm_interrupt_init();
#if defined(CONFIG_PCI)
for (i = I8259_IRQ_OFFSET ; i < I8259_IRQ_OFFSET + NR_8259_INTS ; i++)
- irq_desc[i].handler = &i8259_pic;
+ irq_desc[i].chip = &i8259_pic;
i8259_pic_irq_offset = I8259_IRQ_OFFSET;
i8259_init(0);
out_be32(&intr->main_pri1, 0);
out_be32(&intr->main_pri2, 0);
- /* Initialize irq_desc[i].handler's with mpc52xx_ic. */
+ /* Initialize irq_desc[i].chip's with mpc52xx_ic. */
for (i = 0; i < NR_IRQS; i++) {
- irq_desc[i].handler = &mpc52xx_ic;
+ irq_desc[i].chip = &mpc52xx_ic;
irq_desc[i].status = IRQ_LEVEL;
}
/* All interrupts are level interrupts */
for (i = mv64360_irq_base; i < (mv64360_irq_base + 96); i++) {
irq_desc[i].status |= IRQ_LEVEL;
- irq_desc[i].handler = &mv64360_pic;
+ irq_desc[i].chip = &mv64360_pic;
}
if (ppc_md.progress)
OPENPIC_VEC_IPI+i+offset);
/* IPIs are per-CPU */
irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
- irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
+ irq_desc[OPENPIC_VEC_IPI+i+offset].chip = &open_pic_ipi;
}
#endif
/* Init descriptors */
for (i = offset; i < NumSources + offset; i++)
- irq_desc[i].handler = &open_pic;
+ irq_desc[i].chip = &open_pic;
/* Initialize the spurious interrupt */
if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd);
/* Init descriptors */
for (i = offset; i < NumSources + offset; i++)
- irq_desc[i].handler = &open_pic2;
+ irq_desc[i].chip = &open_pic2;
/* Initialize the spurious interrupt */
if (ppc_md.progress) ppc_md.progress("openpic2: spurious",0x3bd);
ppc_md.get_irq = ppc403_pic_get_irq;
for (i = 0; i < NR_IRQS; i++)
- irq_desc[i].handler = &ppc403_aic;
+ irq_desc[i].chip = &ppc403_aic;
}
/* Attach low-level handlers */
for (i = 0; i < (NR_UICS << 5); ++i) {
- irq_desc[i].handler = &__uic[i >> 5].decl;
+ irq_desc[i].chip = &__uic[i >> 5].decl;
if (is_level_sensitive(i))
irq_desc[i].status |= IRQ_LEVEL;
}
ppc_md.get_irq = xilinx_pic_get_irq;
for (i = 0; i < NR_IRQS; ++i) {
- irq_desc[i].handler = &xilinx_intc;
+ irq_desc[i].chip = &xilinx_intc;
if (XPAR_INTC_0_KIND_OF_INTR & (0x00000001 << i))
irq_desc[i].status &= ~IRQ_LEVEL;
void make_maskreg_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- irq_desc[irq].handler = &maskreg_irq_type;
+ irq_desc[irq].chip = &maskreg_irq_type;
disable_maskreg_irq(irq);
}
/* sanity check first */
if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
/* save the handler in the main description table */
- irq_desc[irq].handler = &bigsur_l1irq_type;
+ irq_desc[irq].chip = &bigsur_l1irq_type;
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
/* sanity check first */
if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
/* save the handler in the main description table */
- irq_desc[irq].handler = &bigsur_l2irq_type;
+ irq_desc[irq].chip = &bigsur_l2irq_type;
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
cqreek_irq_data[14].stat_port = BRIDGE_IDE_INTR_STAT;
cqreek_irq_data[14].bit = 1;
- irq_desc[14].handler = &cqreek_irq_type;
+ irq_desc[14].chip = &cqreek_irq_type;
irq_desc[14].status = IRQ_DISABLED;
irq_desc[14].action = 0;
irq_desc[14].depth = 1;
cqreek_irq_data[10].bit = (1 << 10);
/* XXX: Err... we may need demultiplexer for ISA irq... */
- irq_desc[10].handler = &cqreek_irq_type;
+ irq_desc[10].chip = &cqreek_irq_type;
irq_desc[10].status = IRQ_DISABLED;
irq_desc[10].action = 0;
irq_desc[10].depth = 1;
/* Assign all virtual IRQs to the System ASIC int. handler */
for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
- irq_desc[i].handler = &systemasic_int;
+ irq_desc[i].chip = &systemasic_int;
board_time_init = aica_time_init;
str[i] = ctrl_readb(EC3104_BASE + i);
for (i = EC3104_IRQBASE; i < EC3104_IRQBASE + 32; i++)
- irq_desc[i].handler = &ec3104_int;
+ irq_desc[i].chip = &ec3104_int;
printk("initializing EC3104 \"%.8s\" at %08x, IRQ %d, IRQ base %d\n",
str, EC3104_BASE, EC3104_IRQ, EC3104_IRQBASE);
static void __init make_harp_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- irq_desc[irq].handler = &harp_irq_type;
+ irq_desc[irq].chip = &harp_irq_type;
disable_harp_irq(irq);
}
static void make_mpc1211_irq(unsigned int irq)
{
- irq_desc[irq].handler = &mpc1211_irq_type;
+ irq_desc[irq].chip = &mpc1211_irq_type;
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
static void __init make_od_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- irq_desc[irq].handler = &od_irq_type;
+ irq_desc[irq].chip = &od_irq_type;
disable_od_irq(irq);
}
static void make_hs7751rvoip_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- irq_desc[irq].handler = &hs7751rvoip_irq_type;
+ irq_desc[irq].chip = &hs7751rvoip_irq_type;
disable_hs7751rvoip_irq(irq);
}
static void make_rts7751r2d_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- irq_desc[irq].handler = &rts7751r2d_irq_type;
+ irq_desc[irq].chip = &rts7751r2d_irq_type;
disable_rts7751r2d_irq(irq);
}
void make_systemh_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- irq_desc[irq].handler = &systemh_irq_type;
+ irq_desc[irq].chip = &systemh_irq_type;
disable_systemh_irq(irq);
}
make_intreq_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- irq_desc[irq].handler = &intreq_irq_type;
+ irq_desc[irq].chip = &intreq_irq_type;
disable_intreq_irq(irq);
}
static void __init make_microdev_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- irq_desc[irq].handler = µdev_irq_type;
+ irq_desc[irq].chip = µdev_irq_type;
disable_microdev_irq(irq);
}
outw(0xffff, HD64461_NIMR);
for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) {
- irq_desc[i].handler = &hd64461_irq_type;
+ irq_desc[i].chip = &hd64461_irq_type;
}
setup_irq(CONFIG_HD64461_IRQ, &irq0);
outw(0xffff, HD64465_REG_NIMR); /* mask all interrupts */
for (i = 0; i < HD64465_IRQ_NUM ; i++) {
- irq_desc[HD64465_IRQ_BASE + i].handler = &hd64465_irq_type;
+ irq_desc[HD64465_IRQ_BASE + i].chip = &hd64465_irq_type;
}
setup_irq(CONFIG_HD64465_IRQ, &irq0);
flag = 1;
}
if (flag == 1)
- irq_desc[VOYAGER_IRQ_BASE + i].handler = &voyagergx_irq_type;
+ irq_desc[VOYAGER_IRQ_BASE + i].chip = &voyagergx_irq_type;
}
setup_irq(IRQ_VOYAGER, &irq0);
void make_imask_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- irq_desc[irq].handler = &imask_irq_type;
+ irq_desc[irq].chip = &imask_irq_type;
enable_irq(irq);
}
local_irq_restore(flags);
- irq_desc[irq].handler = &intc2_irq_type;
+ irq_desc[irq].chip = &intc2_irq_type;
disable_intc2_irq(irq);
}
ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */
ipr_data[irq].priority = priority;
- irq_desc[irq].handler = &ipr_irq_type;
+ irq_desc[irq].chip = &ipr_irq_type;
disable_ipr_irq(irq);
}
void make_pint_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- irq_desc[irq].handler = &pint_irq_type;
+ irq_desc[irq].chip = &pint_irq_type;
disable_pint_irq(irq);
}
goto unlock;
seq_printf(p, "%3d: ",i);
seq_printf(p, "%10u ", kstat_irqs(i));
- seq_printf(p, " %14s", irq_desc[i].handler->typename);
+ seq_printf(p, " %14s", irq_desc[i].chip->typename);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
goto unlock;
seq_printf(p, "%3d: ",i);
seq_printf(p, "%10u ", kstat_irqs(i));
- seq_printf(p, " %14s", irq_desc[i].handler->typename);
+ seq_printf(p, " %14s", irq_desc[i].chip->typename);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
void make_intc_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- irq_desc[irq].handler = &intc_irq_type;
+ irq_desc[irq].chip = &intc_irq_type;
disable_intc_irq(irq);
}
/* Set default: per-line enable/disable, priority driven ack/eoi */
for (i = 0; i < NR_INTC_IRQS; i++) {
if (platform_int_priority[i] != NO_PRIORITY) {
- irq_desc[i].handler = &intc_irq_type;
+ irq_desc[i].chip = &intc_irq_type;
}
}
}
for (i=0; i<NR_EXT_IRQS; i++) {
- irq_desc[START_EXT_IRQS + i].handler = &cayman_irq_type;
+ irq_desc[START_EXT_IRQS + i].chip = &cayman_irq_type;
}
/* Setup the SMSC interrupt */
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#endif
- seq_printf(p, " %9s", irq_desc[i].handler->typename);
+ seq_printf(p, " %9s", irq_desc[i].chip->typename);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
data->pre_handler_arg1 = arg1;
data->pre_handler_arg2 = arg2;
- desc->handler = (desc->handler == &sun4u_irq ?
- &sun4u_irq_ack : &sun4v_irq_ack);
+ desc->chip = (desc->chip == &sun4u_irq ?
+ &sun4u_irq_ack : &sun4v_irq_ack);
}
unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
bucket = &ivector_table[ino];
if (!bucket->virt_irq) {
bucket->virt_irq = virt_irq_alloc(__irq(bucket));
- irq_desc[bucket->virt_irq].handler = &sun4u_irq;
+ irq_desc[bucket->virt_irq].chip = &sun4u_irq;
}
desc = irq_desc + bucket->virt_irq;
bucket = &ivector_table[sysino];
if (!bucket->virt_irq) {
bucket->virt_irq = virt_irq_alloc(__irq(bucket));
- irq_desc[bucket->virt_irq].handler = &sun4v_irq;
+ irq_desc[bucket->virt_irq].chip = &sun4v_irq;
}
desc = irq_desc + bucket->virt_irq;
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#endif
- seq_printf(p, " %14s", irq_desc[i].handler->typename);
+ seq_printf(p, " %14s", irq_desc[i].chip->typename);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
irq_desc[TIMER_IRQ].status = IRQ_DISABLED;
irq_desc[TIMER_IRQ].action = NULL;
irq_desc[TIMER_IRQ].depth = 1;
- irq_desc[TIMER_IRQ].handler = &SIGVTALRM_irq_type;
+ irq_desc[TIMER_IRQ].chip = &SIGVTALRM_irq_type;
enable_irq(TIMER_IRQ);
for (i = 1; i < NR_IRQS; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
- irq_desc[i].handler = &normal_irq_type;
+ irq_desc[i].chip = &normal_irq_type;
enable_irq(i);
}
}
int j;
int count = 0;
int num = -1;
- const char *type_name = irq_desc[irq].handler->typename;
+ const char *type_name = irq_desc[irq].chip->typename;
for (j = 0; j < NR_IRQS; j++)
- if (irq_desc[j].handler->typename == type_name){
+ if (irq_desc[j].chip->typename == type_name){
if (irq == j)
num = count;
count++;
irq_desc[base_irq].status = IRQ_DISABLED;
irq_desc[base_irq].action = NULL;
irq_desc[base_irq].depth = 1;
- irq_desc[base_irq].handler = irq_type;
+ irq_desc[base_irq].chip = irq_type;
base_irq += interval;
}
}
{
disable_irq_nosync(irq);
io_apic_irqs &= ~(1<<irq);
- irq_desc[irq].handler = &i8259A_irq_type;
+ irq_desc[irq].chip = &i8259A_irq_type;
enable_irq(irq);
}
/*
* 16 old-style INTA-cycle interrupts:
*/
- irq_desc[i].handler = &i8259A_irq_type;
+ irq_desc[i].chip = &i8259A_irq_type;
} else {
/*
* 'high' PCI IRQs filled in on demand
*/
- irq_desc[i].handler = &no_irq_type;
+ irq_desc[i].chip = &no_irq_type;
}
}
}
#define IOAPIC_EDGE 0
#define IOAPIC_LEVEL 1
-static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
+static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
{
- unsigned idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
+ unsigned idx;
+
+ idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
trigger == IOAPIC_LEVEL)
- irq_desc[idx].handler = &ioapic_level_type;
+ irq_desc[idx].chip = &ioapic_level_type;
else
- irq_desc[idx].handler = &ioapic_edge_type;
+ irq_desc[idx].chip = &ioapic_edge_type;
set_intr_gate(vector, interrupt[idx]);
}
* The timer IRQ doesn't have to know that behind the
* scene we have a 8259A-master in AEOI mode ...
*/
- irq_desc[0].handler = &ioapic_edge_type;
+ irq_desc[0].chip = &ioapic_edge_type;
/*
* Add it to the IO-APIC irq-routing table:
make_8259A_irq(irq);
else
/* Strange. Oh, well.. */
- irq_desc[irq].handler = &no_irq_type;
+ irq_desc[irq].chip = &no_irq_type;
}
}
}
apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
disable_8259A_irq(0);
- irq_desc[0].handler = &lapic_irq_type;
+ irq_desc[0].chip = &lapic_irq_type;
apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
enable_8259A_irq(0);
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#endif
- seq_printf(p, " %14s", irq_desc[i].handler->typename);
+ seq_printf(p, " %14s", irq_desc[i].chip->typename);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
printk("Breaking affinity for irq %i\n", irq);
mask = map;
}
- if (irq_desc[irq].handler->set_affinity)
- irq_desc[irq].handler->set_affinity(irq, mask);
+ if (irq_desc[irq].chip->set_affinity)
+ irq_desc[irq].chip->set_affinity(irq, mask);
else if (irq_desc[irq].action && !(warned++))
printk("Cannot set affinity for irq %i\n", irq);
}
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#endif
- seq_printf(p, " %14s", irq_desc[i].handler->typename);
+ seq_printf(p, " %14s", irq_desc[i].chip->typename);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
int i;
for (i=0; i < XTENSA_NR_IRQS; i++)
- irq_desc[i].handler = &xtensa_irq_type;
+ irq_desc[i].chip = &xtensa_irq_type;
cached_irq_mask = 0;
for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
if (i < GIU_IRQ(GIUINT_HIGH_OFFSET))
- irq_desc[i].handler = &giuint_low_irq_type;
+ irq_desc[i].chip = &giuint_low_irq_type;
else
- irq_desc[i].handler = &giuint_high_irq_type;
+ irq_desc[i].chip = &giuint_high_irq_type;
}
return cascade_irq(GIUINT_IRQ, giu_get_irq);
static void dino_disable_irq(unsigned int irq)
{
- struct dino_device *dino_dev = irq_desc[irq].handler_data;
+ struct dino_device *dino_dev = irq_desc[irq].chip_data;
int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, dino_dev, irq);
static void dino_enable_irq(unsigned int irq)
{
- struct dino_device *dino_dev = irq_desc[irq].handler_data;
+ struct dino_device *dino_dev = irq_desc[irq].chip_data;
int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
u32 tmp;
irq_desc[2].action = &irq2_action;
for (i = 0; i < 16; i++) {
- irq_desc[i].handler = &eisa_interrupt_type;
+ irq_desc[i].chip = &eisa_interrupt_type;
}
EISA_bus = 1;
static void gsc_asic_disable_irq(unsigned int irq)
{
- struct gsc_asic *irq_dev = irq_desc[irq].handler_data;
+ struct gsc_asic *irq_dev = irq_desc[irq].chip_data;
int local_irq = gsc_find_local_irq(irq, irq_dev->global_irq, 32);
u32 imr;
static void gsc_asic_enable_irq(unsigned int irq)
{
- struct gsc_asic *irq_dev = irq_desc[irq].handler_data;
+ struct gsc_asic *irq_dev = irq_desc[irq].chip_data;
int local_irq = gsc_find_local_irq(irq, irq_dev->global_irq, 32);
u32 imr;
if (irq > GSC_IRQ_MAX)
return NO_IRQ;
- irq_desc[irq].handler = type;
- irq_desc[irq].handler_data = data;
+ irq_desc[irq].chip = type;
+ irq_desc[irq].chip_data = data;
return irq++;
}
static struct vector_info *iosapic_get_vector(unsigned int irq)
{
- return irq_desc[irq].handler_data;
+ return irq_desc[irq].chip_data;
}
static void iosapic_disable_irq(unsigned int irq)
#endif
for (i = 0; i < 16; i++) {
- irq_desc[i].handler = &superio_interrupt_type;
+ irq_desc[i].chip = &superio_interrupt_type;
}
/*
spin_lock_irqsave(&irq_desc[pos].lock, flags);
if (cap_id == PCI_CAP_ID_MSIX)
- irq_desc[pos].handler = &msix_irq_type;
+ irq_desc[pos].chip = &msix_irq_type;
else {
if (!mask)
- irq_desc[pos].handler = &msi_irq_wo_maskbit_type;
+ irq_desc[pos].chip = &msi_irq_wo_maskbit_type;
else
- irq_desc[pos].handler = &msi_irq_w_maskbit_type;
+ irq_desc[pos].chip = &msi_irq_w_maskbit_type;
}
spin_unlock_irqrestore(&irq_desc[pos].lock, flags);
}
hs_mapped_irq[irq].sock = sp;
/* insert ourselves as the irq controller */
- hs_mapped_irq[irq].old_handler = irq_desc[irq].handler;
- irq_desc[irq].handler = &hd64465_ss_irq_type;
+ hs_mapped_irq[irq].old_handler = irq_desc[irq].chip;
+ irq_desc[irq].chip = &hd64465_ss_irq_type;
}
return;
/* restore the original irq controller */
- irq_desc[irq].handler = hs_mapped_irq[irq].old_handler;
+ irq_desc[irq].chip = hs_mapped_irq[irq].old_handler;
}
/*============================================================*/
#define mask_irq(irq) \
({ \
irq_desc_t *desc = get_irq_desc(irq); \
- if (desc->handler && desc->handler->disable) \
- desc->handler->disable(irq); \
+ if (desc->chip && desc->chip->disable) \
+ desc->chip->disable(irq); \
})
#define unmask_irq(irq) \
({ \
irq_desc_t *desc = get_irq_desc(irq); \
- if (desc->handler && desc->handler->enable) \
- desc->handler->enable(irq); \
+ if (desc->chip && desc->chip->enable) \
+ desc->chip->enable(irq); \
})
#define ack_irq(irq) \
({ \
irq_desc_t *desc = get_irq_desc(irq); \
- if (desc->handler && desc->handler->ack) \
- desc->handler->ack(irq); \
+ if (desc->chip && desc->chip->ack) \
+ desc->chip->ack(irq); \
})
/* Should we handle this via lost interrupts and IPIs or should we don't care like
* Pad this out to 32 bytes for cache and indexing reasons.
*/
typedef struct irq_desc {
- hw_irq_controller *handler;
- void *handler_data;
+ hw_irq_controller *chip;
+ void *chip_data;
struct irqaction *action; /* IRQ action list */
unsigned int status; /* IRQ status */
unsigned int depth; /* nested irq disables */
spin_lock_irq(&desc->lock);
if (!irq_desc[i].action)
- irq_desc[i].handler->startup(i);
+ irq_desc[i].chip->startup(i);
spin_unlock_irq(&desc->lock);
}
spin_lock_irq(&desc->lock);
if (!desc->action) {
desc->status |= IRQ_AUTODETECT | IRQ_WAITING;
- if (desc->handler->startup(i))
+ if (desc->chip->startup(i))
desc->status |= IRQ_PENDING;
}
spin_unlock_irq(&desc->lock);
/* It triggered already - consider it spurious. */
if (!(status & IRQ_WAITING)) {
desc->status = status & ~IRQ_AUTODETECT;
- desc->handler->shutdown(i);
+ desc->chip->shutdown(i);
} else
if (i < 32)
val |= 1 << i;
mask |= 1 << i;
desc->status = status & ~IRQ_AUTODETECT;
- desc->handler->shutdown(i);
+ desc->chip->shutdown(i);
}
spin_unlock_irq(&desc->lock);
}
nr_irqs++;
}
desc->status = status & ~IRQ_AUTODETECT;
- desc->handler->shutdown(i);
+ desc->chip->shutdown(i);
}
spin_unlock_irq(&desc->lock);
}
irq_desc_t irq_desc[NR_IRQS] __cacheline_aligned = {
[0 ... NR_IRQS-1] = {
.status = IRQ_DISABLED,
- .handler = &no_irq_type,
+ .chip = &no_irq_type,
.lock = SPIN_LOCK_UNLOCKED
}
};
/*
* No locking required for CPU-local interrupts:
*/
- if (desc->handler->ack)
- desc->handler->ack(irq);
+ if (desc->chip->ack)
+ desc->chip->ack(irq);
action_ret = handle_IRQ_event(irq, regs, desc->action);
- desc->handler->end(irq);
+ desc->chip->end(irq);
return 1;
}
spin_lock(&desc->lock);
- if (desc->handler->ack)
- desc->handler->ack(irq);
+ if (desc->chip->ack)
+ desc->chip->ack(irq);
/*
* REPLAY is when Linux resends an IRQ that was dropped earlier
* WAITING is used by probe to mark irqs that are being tested
* The ->end() handler has to deal with interrupts which got
* disabled while the handler was running.
*/
- desc->handler->end(irq);
+ desc->chip->end(irq);
spin_unlock(&desc->lock);
return 1;
spin_lock_irqsave(&desc->lock, flags);
if (!desc->depth++) {
desc->status |= IRQ_DISABLED;
- desc->handler->disable(irq);
+ desc->chip->disable(irq);
}
spin_unlock_irqrestore(&desc->lock, flags);
}
desc->status = status;
if ((status & (IRQ_PENDING | IRQ_REPLAY)) == IRQ_PENDING) {
desc->status = status | IRQ_REPLAY;
- hw_resend_irq(desc->handler,irq);
+ hw_resend_irq(desc->chip,irq);
}
- desc->handler->enable(irq);
+ desc->chip->enable(irq);
/* fall-through */
}
default:
if (irq >= NR_IRQS)
return -EINVAL;
- if (desc->handler == &no_irq_type)
+ if (desc->chip == &no_irq_type)
return -ENOSYS;
/*
* Some drivers like serial.c use request_irq() heavily,
desc->depth = 0;
desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT |
IRQ_WAITING | IRQ_INPROGRESS);
- if (desc->handler->startup)
- desc->handler->startup(irq);
+ if (desc->chip->startup)
+ desc->chip->startup(irq);
else
- desc->handler->enable(irq);
+ desc->chip->enable(irq);
}
spin_unlock_irqrestore(&desc->lock,flags);
/* Currently used only by UML, might disappear one day.*/
#ifdef CONFIG_IRQ_RELEASE_METHOD
- if (desc->handler->release)
- desc->handler->release(irq, dev_id);
+ if (desc->chip->release)
+ desc->chip->release(irq, dev_id);
#endif
if (!desc->action) {
desc->status |= IRQ_DISABLED;
- if (desc->handler->shutdown)
- desc->handler->shutdown(irq);
+ if (desc->chip->shutdown)
+ desc->chip->shutdown(irq);
else
- desc->handler->disable(irq);
+ desc->chip->disable(irq);
}
spin_unlock_irqrestore(&desc->lock,flags);
unregister_handler_proc(irq, action);
if (unlikely(cpus_empty(pending_irq_cpumask[irq])))
return;
- if (!desc->handler->set_affinity)
+ if (!desc->chip->set_affinity)
return;
assert_spin_locked(&desc->lock);
*/
if (likely(!cpus_empty(tmp))) {
if (likely(!(desc->status & IRQ_DISABLED)))
- desc->handler->disable(irq);
+ desc->chip->disable(irq);
- desc->handler->set_affinity(irq,tmp);
+ desc->chip->set_affinity(irq,tmp);
if (likely(!(desc->status & IRQ_DISABLED)))
- desc->handler->enable(irq);
+ desc->chip->enable(irq);
}
cpus_clear(pending_irq_cpumask[irq]);
}
{
set_balance_irq_affinity(irq, mask_val);
irq_affinity[irq] = mask_val;
- irq_desc[irq].handler->set_affinity(irq, mask_val);
+ irq_desc[irq].chip->set_affinity(irq, mask_val);
}
#endif
unsigned int irq = (int)(long)data, full_count = count, err;
cpumask_t new_value, tmp;
- if (!irq_desc[irq].handler->set_affinity || no_irq_affinity)
+ if (!irq_desc[irq].chip->set_affinity || no_irq_affinity)
return -EIO;
err = cpumask_parse(buffer, count, new_value);
char name [MAX_NAMELEN];
if (!root_irq_dir ||
- (irq_desc[irq].handler == &no_irq_type) ||
+ (irq_desc[irq].chip == &no_irq_type) ||
irq_dir[irq])
return;
* IRQ controller clean up too
*/
if(work)
- desc->handler->end(i);
+ desc->chip->end(i);
spin_unlock(&desc->lock);
}
/* So the caller can adjust the irq error counts */
*/
printk(KERN_EMERG "Disabling IRQ #%d\n", irq);
desc->status |= IRQ_DISABLED;
- desc->handler->disable(irq);
+ desc->chip->disable(irq);
}
desc->irqs_unhandled = 0;
}
projects / linux-2.6-omap-h63xx.git / commitdiff