/* do whatever is necessary to start controller */
for (i = 0; i < ARRAY_SIZE(pController->txCppi); i++) {
- pController->txCppi[i].bTransmit = TRUE;
+ pController->txCppi[i].transmit = TRUE;
pController->txCppi[i].chNo = i;
}
for (i = 0; i < ARRAY_SIZE(pController->rxCppi); i++) {
- pController->rxCppi[i].bTransmit = FALSE;
+ pController->rxCppi[i].transmit = FALSE;
pController->rxCppi[i].chNo = i;
}
static struct dma_channel *
cppi_channel_allocate(struct dma_controller *c,
struct musb_hw_ep *ep,
- u8 bTransmit)
+ u8 transmit)
{
struct cppi *pController;
u8 chNum;
/* return the corresponding CPPI Channel Handle, and
* probably disable the non-CPPI irq until we need it.
*/
- if (bTransmit) {
+ if (transmit) {
if (local_end > ARRAY_SIZE(pController->txCppi)) {
DBG(1, "no %cX DMA channel for ep%d\n", 'T', local_end);
return NULL;
*/
if (otgCh->hw_ep)
DBG(1, "re-allocating DMA%d %cX channel %p\n",
- chNum, bTransmit ? 'T' : 'R', otgCh);
+ chNum, transmit ? 'T' : 'R', otgCh);
otgCh->hw_ep = ep;
otgCh->Channel.status = MGC_DMA_STATUS_FREE;
- DBG(4, "Allocate CPPI%d %cX\n", chNum, bTransmit ? 'T' : 'R');
+ DBG(4, "Allocate CPPI%d %cX\n", chNum, transmit ? 'T' : 'R');
otgCh->Channel.private_data = otgCh;
return &otgCh->Channel;
}
tibase = c->pController->pCoreBase - DAVINCI_BASE_OFFSET;
if (!c->hw_ep)
DBG(1, "releasing idle DMA channel %p\n", c);
- else if (!c->bTransmit)
+ else if (!c->transmit)
core_rxirq_enable(tibase, epnum);
/* for now, leave its cppi IRQ enabled (we won't trigger it) */
case MGC_DMA_STATUS_CORE_ABORT:
/* fault irq handler should have handled cleanup */
WARN("%cX DMA%d not cleaned up after abort!\n",
- otgChannel->bTransmit ? 'T' : 'R',
+ otgChannel->transmit ? 'T' : 'R',
otgChannel->chNo);
//WARN_ON(1);
break;
case MGC_DMA_STATUS_BUSY:
WARN("program active channel? %cX DMA%d\n",
- otgChannel->bTransmit ? 'T' : 'R',
+ otgChannel->transmit ? 'T' : 'R',
otgChannel->chNo);
//WARN_ON(1);
break;
case MGC_DMA_STATUS_UNKNOWN:
DBG(1, "%cX DMA%d not allocated!\n",
- otgChannel->bTransmit ? 'T' : 'R',
+ otgChannel->transmit ? 'T' : 'R',
otgChannel->chNo);
/* FALLTHROUGH */
case MGC_DMA_STATUS_FREE:
otgChannel->transferSize = dwLength;
/* TX channel? or RX? */
- if (otgChannel->bTransmit)
+ if (otgChannel->transmit)
cppi_next_tx_segment(musb, otgChannel);
else
cppi_next_rx_segment(musb, otgChannel, mode);
return -EINVAL;
}
- if (!otgCh->bTransmit && otgCh->activeQueueHead)
+ if (!otgCh->transmit && otgCh->activeQueueHead)
cppi_dump_rxq(3, "/abort", otgCh);
mbase = pController->pCoreBase;
*/
musb_ep_select(mbase, chNum + 1);
- if (otgCh->bTransmit) {
+ if (otgCh->transmit) {
struct cppi_tx_stateram *__iomem txState;
int enabled;
u16 wMaxPacketSize;
u8 bIndex;
u8 epnum;
- u8 bTransmit;
+ u8 transmit;
};
struct musb_dma_controller {
}
static struct dma_channel* dma_channel_allocate(struct dma_controller *c,
- struct musb_hw_ep *hw_ep, u8 bTransmit)
+ struct musb_hw_ep *hw_ep, u8 transmit)
{
u8 bBit;
struct dma_channel *pChannel = NULL;
pImplChannel->pController = pController;
pImplChannel->bIndex = bBit;
pImplChannel->epnum = hw_ep->epnum;
- pImplChannel->bTransmit = bTransmit;
+ pImplChannel->transmit = transmit;
pChannel = &(pImplChannel->Channel);
pChannel->private_data = pImplChannel;
pChannel->status = MGC_DMA_STATUS_FREE;
pChannel->max_len = 0x10000;
/* Tx => mode 1; Rx => mode 0 */
- pChannel->desired_mode = bTransmit;
+ pChannel->desired_mode = transmit;
pChannel->actual_len = 0;
break;
}
csr |= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
| (1 << MUSB_HSDMA_ENABLE_SHIFT)
| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
- | (pImplChannel->bTransmit ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) : 0);
+ | (pImplChannel->transmit ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) : 0);
/* address/count */
musb_writel(mbase,
DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
pImplChannel->epnum,
- pImplChannel->bTransmit ? "Tx" : "Rx",
+ pImplChannel->transmit ? "Tx" : "Rx",
packet_sz, dma_addr, dwLength, mode);
BUG_ON(pChannel->status == MGC_DMA_STATUS_UNKNOWN ||
u16 csr;
if (pChannel->status == MGC_DMA_STATUS_BUSY) {
- if (pImplChannel->bTransmit) {
+ if (pImplChannel->transmit) {
csr = musb_readw(mbase,
MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR));
/* completed */
if ((devctl & MUSB_DEVCTL_HM)
- && (pImplChannel->bTransmit)
+ && (pImplChannel->transmit)
&& ((pChannel->desired_mode == 0)
|| (pChannel->actual_len &
(pImplChannel->wMaxPacketSize - 1)))
musb_dma_completion(
pController->pDmaPrivate,
pImplChannel->epnum,
- pImplChannel->bTransmit);
+ pImplChannel->transmit);
}
}
}