[WATCHDOG] i6300esb-set_correct_reload_register_bit

This patch writes into bit 8 of the reload register to perform the
correct 'Reload Sequence' instead of writing into bit 4 of Watchdog for
Intel 6300ESB chipset.

Signed-off-by: Naveen Gupta <ngupta@google.com>
Signed-off-by: David Hardeman <david@2gen.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Signed-off-by: Andrew Morton <akpm@osdl.org>

diff --git a/drivers/char/watchdog/i6300esb.c b/drivers/char/watchdog/i6300esb.c
index f0e96fbd6489ef6948b883aacbfd91be2264af6c..c04b246858ae416993b73d08a6bbf936c16ea9f6 100644 (file)
--- a/drivers/char/watchdog/i6300esb.c
+++ b/drivers/char/watchdog/i6300esb.c
@@ -109,7 +109,7 @@ static int esb_timer_stop(void)
        spin_lock(&esb_lock);
        /* First, reset timers as suggested by the docs */
        esb_unlock_registers();
-       writew(0x10, ESB_RELOAD_REG);
+       writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
        /* Then disable the WDT */
        pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0);
        pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val);
@@ -123,7 +123,7 @@ static void esb_timer_keepalive(void)
 {
        spin_lock(&esb_lock);
        esb_unlock_registers();
-       writew(0x10, ESB_RELOAD_REG);
+       writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
         /* FIXME: Do we need to flush anything here? */
        spin_unlock(&esb_lock);
 }
@@ -153,7 +153,7 @@ static int esb_timer_set_heartbeat(int time)
 
         /* Reload */
        esb_unlock_registers();
-       writew(0x10, ESB_RELOAD_REG);
+       writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
 
        /* FIXME: Do we need to flush everything out? */
 

diff --git a/drivers/char/watchdog/i6300esb.h b/drivers/char/watchdog/i6300esb.h
index b5b47e3dda1a87db5839807e0c9662b7441fe615..20c923bbb1c9be1edf24a8b885ffe4332bdc5979 100644 (file)
--- a/drivers/char/watchdog/i6300esb.h
+++ b/drivers/char/watchdog/i6300esb.h
@@ -54,6 +54,8 @@
 #define ESB_WDT_FREQ    ( 0x01 << 2 )   /* Decrement frequency               */
 #define ESB_WDT_INTTYPE ( 0x11 << 0 )   /* Interrupt type on timer1 timeout  */
 
+/* Reload register bits */
+#define ESB_WDT_RELOAD ( 0x01 << 8 )    /* prevent timeout                   */
 
 /*
  * Some magic constants