[MIPS] SMTC: Fix crash if # of TC's > # of VPE's after pt_regs irq cleanup.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index 417c08ac76eb52e393a617ab0a5871db07413475..f10b6a19f8bf7b672242dbf2dcf9bf1f495c7c13 100644 (file)
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -83,7 +83,10 @@ FEXPORT(syscall_exit)
 FEXPORT(restore_all)                   # restore full frame
 #ifdef CONFIG_MIPS_MT_SMTC
 /* Detect and execute deferred IPI "interrupts" */
+       LONG_L  s0, TI_REGS($28)
+       LONG_S  sp, TI_REGS($28)
        jal     deferred_smtc_ipi
+       LONG_S  s0, TI_REGS($28)
 /* Re-arm any temporarily masked interrupts not explicitly "acked" */
        mfc0    v0, CP0_TCSTATUS
        ori     v1, v0, TCSTATUS_IXMT

diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S
index 1cb9441f1474f76692319df943b8ee20b4bf994a..921207c4a83c115ac77dfeadfe6c25bc31fb9d58 100644 (file)
--- a/arch/mips/kernel/smtc-asm.S
+++ b/arch/mips/kernel/smtc-asm.S
@@ -101,7 +101,9 @@ FEXPORT(__smtc_ipi_vector)
        lw      t0,PT_PADSLOT5(sp)
        /* Argument from sender passed in stack pad slot 4 */
        lw      a0,PT_PADSLOT4(sp)
-       PTR_LA  ra, _ret_from_irq
+       LONG_L  s0, TI_REGS($28)
+       LONG_S  sp, TI_REGS($28)
+       PTR_LA  ra, ret_from_irq
        jr      t0
 
 /*
@@ -119,7 +121,10 @@ LEAF(self_ipi)
        subu    t1,sp,PT_SIZE
        sw      ra,PT_EPC(t1)
        sw      a0,PT_PADSLOT4(t1)
+       LONG_L  s0, TI_REGS($28)
+       LONG_S  sp, TI_REGS($28)
        la      t2,ipi_decode
+       LONG_S  s0, TI_REGS($28)
        sw      t2,PT_PADSLOT5(t1)
        /* Save pre-disable value of TCStatus */
        sw      t0,PT_TCSTATUS(t1)