]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[POWERPC] cell: PMU register macros
authorKevin Corry <kevcorry@us.ibm.com>
Mon, 20 Nov 2006 17:45:13 +0000 (18:45 +0100)
committerPaul Mackerras <paulus@samba.org>
Mon, 4 Dec 2006 09:40:09 +0000 (20:40 +1100)
More macros for manipulating bits in the Cell PMU control registers.

Signed-off-by: Kevin Corry <kevcorry@us.ibm.com>
Signed-off-by: Carl Love <carll@us.ibm.com>
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
arch/powerpc/platforms/cell/cbe_regs.h

index 91083f51a0cb1ce034c567b17a50f51dc1015cc8..bc94e664c6173723a97ac06f19f6438a2e2c01b8 100644 (file)
 /* Macros for the pm_control register. */
 #define CBE_PM_16BIT_CTR(ctr)                  (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
 #define CBE_PM_ENABLE_PERF_MON                 0x80000000
-
+#define CBE_PM_STOP_AT_MAX                     0x40000000
+#define CBE_PM_TRACE_MODE_GET(pm_control)      (((pm_control) >> 28) & 0x3)
+#define CBE_PM_TRACE_MODE_SET(mode)            (((mode)  & 0x3) << 28)
+#define CBE_PM_COUNT_MODE_SET(count)           (((count) & 0x3) << 18)
+#define CBE_PM_FREEZE_ALL_CTRS                 0x00100000
+#define CBE_PM_ENABLE_EXT_TRACE                        0x00008000
+
+/* Macros for the trace_address register. */
+#define CBE_PM_TRACE_BUF_FULL                  0x00000800
+#define CBE_PM_TRACE_BUF_EMPTY                 0x00000400
+#define CBE_PM_TRACE_BUF_DATA_COUNT(ta)                ((ta) & 0x3ff)
+#define CBE_PM_TRACE_BUF_MAX_COUNT             0x400
+
+/* Macros for the pm07_control registers. */
+#define CBE_PM_CTR_INPUT_MUX(pm07_control)     (((pm07_control) >> 26) & 0x3f)
+#define CBE_PM_CTR_INPUT_CONTROL               0x02000000
+#define CBE_PM_CTR_POLARITY                    0x01000000
+#define CBE_PM_CTR_COUNT_CYCLES                        0x00800000
+#define CBE_PM_CTR_ENABLE                      0x00400000
+
+/* Macros for the pm_status register. */
+#define CBE_PM_CTR_OVERFLOW_INTR(ctr)          (1 << (31 - ((ctr) & 7)))
 
 union spe_reg {
        u64 val;