]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[POWERPC] Add device trees for lite5200 and lite5200b eval boards
authorGrant Likely <grant.likely@secretlab.ca>
Mon, 27 Nov 2006 21:16:29 +0000 (14:16 -0700)
committerPaul Mackerras <paulus@samba.org>
Mon, 4 Dec 2006 09:41:46 +0000 (20:41 +1100)
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Sylvain Munaut <tnt@246tNt.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
arch/powerpc/boot/dts/lite5200.dts [new file with mode: 0644]
arch/powerpc/boot/dts/lite5200b.dts [new file with mode: 0644]

diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
new file mode 100644 (file)
index 0000000..8bc0d25
--- /dev/null
@@ -0,0 +1,313 @@
+/*
+ * Lite5200 board Device Tree Source
+ *
+ * Copyright 2006 Secret Lab Technologies Ltd.
+ * Grant Likely <grant.likely@secretlab.ca>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/ {
+       model = "Lite5200";
+       compatible = "lite5200\0lite52xx\0mpc5200\0mpc52xx";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       cpus {
+               #cpus = <1>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,5200@0 {
+                       device_type = "cpu";
+                       reg = <0>;
+                       d-cache-line-size = <20>;
+                       i-cache-line-size = <20>;
+                       d-cache-size = <4000>;          // L1, 16K
+                       i-cache-size = <4000>;          // L1, 16K
+                       timebase-frequency = <0>;       // from bootloader
+                       bus-frequency = <0>;            // from bootloader
+                       clock-frequency = <0>;          // from bootloader
+                       32-bit;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <00000000 04000000>;      // 64MB
+       };
+
+       soc5200@f0000000 {
+               #interrupt-cells = <3>;
+               device_type = "soc";
+               ranges = <0 f0000000 f0010000>;
+               reg = <f0000000 00010000>;
+               bus-frequency = <0>;            // from bootloader
+
+               cdm@200 {
+                       compatible = "mpc5200-cdm\0mpc52xx-cdm";
+                       reg = <200 38>;
+               };
+
+               pic@500 {
+                       // 5200 interrupts are encoded into two levels;
+                       linux,phandle = <500>;
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+                       device_type = "interrupt-controller";
+                       compatible = "mpc5200-pic\0mpc52xx-pic";
+                       reg = <500 80>;
+                       built-in;
+               };
+
+               gpt@600 {       // General Purpose Timer
+                       compatible = "mpc5200-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <600 10>;
+                       interrupts = <1 9 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@610 {       // General Purpose Timer
+                       compatible = "mpc5200-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <610 10>;
+                       interrupts = <1 a 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@620 {       // General Purpose Timer
+                       compatible = "mpc5200-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <620 10>;
+                       interrupts = <1 b 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@630 {       // General Purpose Timer
+                       compatible = "mpc5200-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <630 10>;
+                       interrupts = <1 c 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@640 {       // General Purpose Timer
+                       compatible = "mpc5200-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <640 10>;
+                       interrupts = <1 d 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@650 {       // General Purpose Timer
+                       compatible = "mpc5200-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <650 10>;
+                       interrupts = <1 e 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@660 {       // General Purpose Timer
+                       compatible = "mpc5200-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <660 10>;
+                       interrupts = <1 f 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@670 {       // General Purpose Timer
+                       compatible = "mpc5200-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <670 10>;
+                       interrupts = <1 10 0>;
+                       interrupt-parent = <500>;
+               };
+
+               rtc@800 {       // Real time clock
+                       compatible = "mpc5200-rtc\0mpc52xx-rtc";
+                       device_type = "rtc";
+                       reg = <800 100>;
+                       interrupts = <1 5 0 1 6 0>;
+                       interrupt-parent = <500>;
+               };
+
+               mscan@900 {
+                       device_type = "mscan";
+                       compatible = "mpc5200-mscan\0mpc52xx-mscan";
+                       interrupts = <2 11 0>;
+                       interrupt-parent = <500>;
+                       reg = <900 80>;
+               };
+
+               mscan@980 {
+                       device_type = "mscan";
+                       compatible = "mpc5200-mscan\0mpc52xx-mscan";
+                       interrupts = <1 12 0>;
+                       interrupt-parent = <500>;
+                       reg = <980 80>;
+               };
+
+               gpio@b00 {
+                       compatible = "mpc5200-gpio\0mpc52xx-gpio";
+                       reg = <b00 40>;
+                       interrupts = <1 7 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpio-wkup@b00 {
+                       compatible = "mpc5200-gpio-wkup\0mpc52xx-gpio-wkup";
+                       reg = <c00 40>;
+                       interrupts = <1 8 0 0 3 0>;
+                       interrupt-parent = <500>;
+               };
+
+               pci@0d00 {
+                       #interrupt-cells = <1>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       compatible = "mpc5200-pci\0mpc52xx-pci";
+                       reg = <d00 100>;
+                       interrupt-map-mask = <f800 0 0 7>;
+                       interrupt-map = <c000 0 0 1 500 0 0 3
+                                        c000 0 0 2 500 0 0 3
+                                        c000 0 0 3 500 0 0 3
+                                        c000 0 0 4 500 0 0 3>;
+                       clock-frequency = <0>; // From boot loader
+                       interrupts = <2 8 0 2 9 0 2 a 0>;
+                       interrupt-parent = <500>;
+                       bus-range = <0 0>;
+                       ranges = <42000000 0 80000000 80000000 0 20000000
+                                 02000000 0 a0000000 a0000000 0 10000000
+                                 01000000 0 00000000 b0000000 0 01000000>;
+               };
+
+               spi@f00 {
+                       device_type = "spi";
+                       compatible = "mpc5200-spi\0mpc52xx-spi";
+                       reg = <f00 20>;
+                       interrupts = <2 d 0 2 e 0>;
+                       interrupt-parent = <500>;
+               };
+
+               usb@1000 {
+                       device_type = "usb-ohci-be";
+                       compatible = "mpc5200-ohci\0mpc52xx-ohci\0ohci-be";
+                       reg = <1000 ff>;
+                       interrupts = <2 6 0>;
+                       interrupt-parent = <500>;
+               };
+
+               bestcomm@1200 {
+                       device_type = "dma-controller";
+                       compatible = "mpc5200-bestcomm\0mpc52xx-bestcomm";
+                       reg = <1200 80>;
+                       interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
+                                     3 4 0  3 5 0  3 6 0  3 7 0
+                                     3 8 0  3 9 0  3 a 0  3 b 0
+                                     3 c 0  3 d 0  3 e 0  3 f 0>;
+                       interrupt-parent = <500>;
+               };
+
+               xlb@1f00 {
+                       compatible = "mpc5200-xlb\0mpc52xx-xlb";
+                       reg = <1f00 100>;
+               };
+
+               serial@2000 {           // PSC1
+                       device_type = "serial";
+                       compatible = "mpc5200-psc-uart\0mpc52xx-psc-uart";
+                       port-number = <0>;  // Logical port assignment
+                       reg = <2000 100>;
+                       interrupts = <2 1 0>;
+                       interrupt-parent = <500>;
+               };
+
+               // PSC2 in spi mode example
+               spi@2200 {              // PSC2
+                       device_type = "spi";
+                       compatible = "mpc5200-psc-spi\0mpc52xx-psc-spi";
+                       reg = <2200 100>;
+                       interrupts = <2 2 0>;
+                       interrupt-parent = <500>;
+               };
+
+               // PSC3 in CODEC mode example
+               i2s@2400 {              // PSC3
+                       device_type = "i2s";
+                       compatible = "mpc5200-psc-i2s\0mpc52xx-psc-i2s";
+                       reg = <2400 100>;
+                       interrupts = <2 3 0>;
+                       interrupt-parent = <500>;
+               };
+
+               // PSC4 unconfigured
+               //serial@2600 {         // PSC4
+               //      device_type = "serial";
+               //      compatible = "mpc5200-psc-uart\0mpc52xx-psc-uart";
+               //      reg = <2600 100>;
+               //      interrupts = <2 b 0>;
+               //      interrupt-parent = <500>;
+               //};
+
+               // PSC5 unconfigured
+               //serial@2800 {         // PSC5
+               //      device_type = "serial";
+               //      compatible = "mpc5200-psc-uart\0mpc52xx-psc-uart";
+               //      reg = <2800 100>;
+               //      interrupts = <2 c 0>;
+               //      interrupt-parent = <500>;
+               //};
+
+               // PSC6 in AC97 mode example
+               ac97@2c00 {             // PSC6
+                       device_type = "ac97";
+                       compatible = "mpc5200-psc-ac97\0mpc52xx-psc-ac97";
+                       reg = <2c00 100>;
+                       interrupts = <2 4 0>;
+                       interrupt-parent = <500>;
+               };
+
+               ethernet@3000 {
+                       device_type = "network";
+                       compatible = "mpc5200-fec\0mpc52xx-fec";
+                       reg = <3000 800>;
+                       mac-address = [ 02 03 04 05 06 07 ]; // Bad!
+                       interrupts = <2 5 0>;
+                       interrupt-parent = <500>;
+               };
+
+               ata@3a00 {
+                       device_type = "ata";
+                       compatible = "mpc5200-ata\0mpc52xx-ata";
+                       reg = <3a00 100>;
+                       interrupts = <2 7 0>;
+                       interrupt-parent = <500>;
+               };
+
+               i2c@3d00 {
+                       device_type = "i2c";
+                       compatible = "mpc5200-i2c\0mpc52xx-i2c";
+                       reg = <3d00 40>;
+                       interrupts = <2 f 0>;
+                       interrupt-parent = <500>;
+               };
+
+               i2c@3d40 {
+                       device_type = "i2c";
+                       compatible = "mpc5200-i2c\0mpc52xx-i2c";
+                       reg = <3d40 40>;
+                       interrupts = <2 10 0>;
+                       interrupt-parent = <500>;
+               };
+               sram@8000 {
+                       device_type = "sram";
+                       compatible = "mpc5200-sram\0mpc52xx-sram\0sram";
+                       reg = <8000 4000>;
+               };
+       };
+};
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
new file mode 100644 (file)
index 0000000..81cb764
--- /dev/null
@@ -0,0 +1,318 @@
+/*
+ * Lite5200B board Device Tree Source
+ *
+ * Copyright 2006 Secret Lab Technologies Ltd.
+ * Grant Likely <grant.likely@secretlab.ca>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/ {
+       model = "Lite5200b";
+       compatible = "lite5200b\0lite52xx\0mpc5200b\0mpc52xx";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       cpus {
+               #cpus = <1>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,5200@0 {
+                       device_type = "cpu";
+                       reg = <0>;
+                       d-cache-line-size = <20>;
+                       i-cache-line-size = <20>;
+                       d-cache-size = <4000>;          // L1, 16K
+                       i-cache-size = <4000>;          // L1, 16K
+                       timebase-frequency = <0>;       // from bootloader
+                       bus-frequency = <0>;            // from bootloader
+                       clock-frequency = <0>;          // from bootloader
+                       32-bit;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <00000000 10000000>;      // 256MB
+       };
+
+       soc5200@f0000000 {
+               #interrupt-cells = <3>;
+               device_type = "soc";
+               ranges = <0 f0000000 f0010000>;
+               reg = <f0000000 00010000>;
+               bus-frequency = <0>;            // from bootloader
+
+               cdm@200 {
+                       compatible = "mpc5200b-cdm\0mpc52xx-cdm";
+                       reg = <200 38>;
+               };
+
+               pic@500 {
+                       // 5200 interrupts are encoded into two levels;
+                       linux,phandle = <500>;
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+                       device_type = "interrupt-controller";
+                       compatible = "mpc5200b-pic\0mpc52xx-pic";
+                       reg = <500 80>;
+                       built-in;
+               };
+
+               gpt@600 {       // General Purpose Timer
+                       compatible = "mpc5200b-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <600 10>;
+                       interrupts = <1 9 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@610 {       // General Purpose Timer
+                       compatible = "mpc5200b-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <610 10>;
+                       interrupts = <1 a 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@620 {       // General Purpose Timer
+                       compatible = "mpc5200b-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <620 10>;
+                       interrupts = <1 b 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@630 {       // General Purpose Timer
+                       compatible = "mpc5200b-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <630 10>;
+                       interrupts = <1 c 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@640 {       // General Purpose Timer
+                       compatible = "mpc5200b-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <640 10>;
+                       interrupts = <1 d 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@650 {       // General Purpose Timer
+                       compatible = "mpc5200b-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <650 10>;
+                       interrupts = <1 e 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@660 {       // General Purpose Timer
+                       compatible = "mpc5200b-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <660 10>;
+                       interrupts = <1 f 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpt@670 {       // General Purpose Timer
+                       compatible = "mpc5200b-gpt\0mpc52xx-gpt";
+                       device_type = "gpt";
+                       reg = <670 10>;
+                       interrupts = <1 10 0>;
+                       interrupt-parent = <500>;
+               };
+
+               rtc@800 {       // Real time clock
+                       compatible = "mpc5200b-rtc\0mpc52xx-rtc";
+                       device_type = "rtc";
+                       reg = <800 100>;
+                       interrupts = <1 5 0 1 6 0>;
+                       interrupt-parent = <500>;
+               };
+
+               mscan@900 {
+                       device_type = "mscan";
+                       compatible = "mpc5200b-mscan\0mpc52xx-mscan";
+                       interrupts = <2 11 0>;
+                       interrupt-parent = <500>;
+                       reg = <900 80>;
+               };
+
+               mscan@980 {
+                       device_type = "mscan";
+                       compatible = "mpc5200b-mscan\0mpc52xx-mscan";
+                       interrupts = <1 12 0>;
+                       interrupt-parent = <500>;
+                       reg = <980 80>;
+               };
+
+               gpio@b00 {
+                       compatible = "mpc5200b-gpio\0mpc52xx-gpio";
+                       reg = <b00 40>;
+                       interrupts = <1 7 0>;
+                       interrupt-parent = <500>;
+               };
+
+               gpio-wkup@b00 {
+                       compatible = "mpc5200b-gpio-wkup\0mpc52xx-gpio-wkup";
+                       reg = <c00 40>;
+                       interrupts = <1 8 0 0 3 0>;
+                       interrupt-parent = <500>;
+               };
+
+               pci@0d00 {
+                       #interrupt-cells = <1>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       compatible = "mpc5200b-pci\0mpc52xx-pci";
+                       reg = <d00 100>;
+                       interrupt-map-mask = <f800 0 0 7>;
+                       interrupt-map = <c000 0 0 1 500 0 0 3 // 1st slot
+                                        c000 0 0 2 500 1 1 3
+                                        c000 0 0 3 500 1 2 3
+                                        c000 0 0 4 500 1 3 3
+
+                                        c800 0 0 1 500 1 1 3 // 2nd slot
+                                        c800 0 0 2 500 1 2 3
+                                        c800 0 0 3 500 1 3 3
+                                        c800 0 0 4 500 0 0 3>;
+                       clock-frequency = <0>; // From boot loader
+                       interrupts = <2 8 0 2 9 0 2 a 0>;
+                       interrupt-parent = <500>;
+                       bus-range = <0 0>;
+                       ranges = <42000000 0 80000000 80000000 0 20000000
+                                 02000000 0 a0000000 a0000000 0 10000000
+                                 01000000 0 00000000 b0000000 0 01000000>;
+               };
+
+               spi@f00 {
+                       device_type = "spi";
+                       compatible = "mpc5200b-spi\0mpc52xx-spi";
+                       reg = <f00 20>;
+                       interrupts = <2 d 0 2 e 0>;
+                       interrupt-parent = <500>;
+               };
+
+               usb@1000 {
+                       device_type = "usb-ohci-be";
+                       compatible = "mpc5200b-ohci\0mpc52xx-ohci\0ohci-be";
+                       reg = <1000 ff>;
+                       interrupts = <2 6 0>;
+                       interrupt-parent = <500>;
+               };
+
+               bestcomm@1200 {
+                       device_type = "dma-controller";
+                       compatible = "mpc5200b-bestcomm\0mpc52xx-bestcomm";
+                       reg = <1200 80>;
+                       interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
+                                     3 4 0  3 5 0  3 6 0  3 7 0
+                                     3 8 0  3 9 0  3 a 0  3 b 0
+                                     3 c 0  3 d 0  3 e 0  3 f 0>;
+                       interrupt-parent = <500>;
+               };
+
+               xlb@1f00 {
+                       compatible = "mpc5200b-xlb\0mpc52xx-xlb";
+                       reg = <1f00 100>;
+               };
+
+               serial@2000 {           // PSC1
+                       device_type = "serial";
+                       compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart";
+                       port-number = <0>;  // Logical port assignment
+                       reg = <2000 100>;
+                       interrupts = <2 1 0>;
+                       interrupt-parent = <500>;
+               };
+
+               // PSC2 in spi mode example
+               spi@2200 {              // PSC2
+                       device_type = "spi";
+                       compatible = "mpc5200b-psc-spi\0mpc52xx-psc-spi";
+                       reg = <2200 100>;
+                       interrupts = <2 2 0>;
+                       interrupt-parent = <500>;
+               };
+
+               // PSC3 in CODEC mode example
+               i2s@2400 {              // PSC3
+                       device_type = "i2s";
+                       compatible = "mpc5200b-psc-i2s\0mpc52xx-psc-i2s";
+                       reg = <2400 100>;
+                       interrupts = <2 3 0>;
+                       interrupt-parent = <500>;
+               };
+
+               // PSC4 unconfigured
+               //serial@2600 {         // PSC4
+               //      device_type = "serial";
+               //      compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart";
+               //      reg = <2600 100>;
+               //      interrupts = <2 b 0>;
+               //      interrupt-parent = <500>;
+               //};
+
+               // PSC5 unconfigured
+               //serial@2800 {         // PSC5
+               //      device_type = "serial";
+               //      compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart";
+               //      reg = <2800 100>;
+               //      interrupts = <2 c 0>;
+               //      interrupt-parent = <500>;
+               //};
+
+               // PSC6 in AC97 mode example
+               ac97@2c00 {             // PSC6
+                       device_type = "ac97";
+                       compatible = "mpc5200b-psc-ac97\0mpc52xx-psc-ac97";
+                       reg = <2c00 100>;
+                       interrupts = <2 4 0>;
+                       interrupt-parent = <500>;
+               };
+
+               ethernet@3000 {
+                       device_type = "network";
+                       compatible = "mpc5200b-fec\0mpc52xx-fec";
+                       reg = <3000 800>;
+                       mac-address = [ 02 03 04 05 06 07 ]; // Bad!
+                       interrupts = <2 5 0>;
+                       interrupt-parent = <500>;
+               };
+
+               ata@3a00 {
+                       device_type = "ata";
+                       compatible = "mpc5200b-ata\0mpc52xx-ata";
+                       reg = <3a00 100>;
+                       interrupts = <2 7 0>;
+                       interrupt-parent = <500>;
+               };
+
+               i2c@3d00 {
+                       device_type = "i2c";
+                       compatible = "mpc5200b-i2c\0mpc52xx-i2c";
+                       reg = <3d00 40>;
+                       interrupts = <2 f 0>;
+                       interrupt-parent = <500>;
+               };
+
+               i2c@3d40 {
+                       device_type = "i2c";
+                       compatible = "mpc5200b-i2c\0mpc52xx-i2c";
+                       reg = <3d40 40>;
+                       interrupts = <2 10 0>;
+                       interrupt-parent = <500>;
+               };
+               sram@8000 {
+                       device_type = "sram";
+                       compatible = "mpc5200b-sram\0mpc52xx-sram\0sram";
+                       reg = <8000 4000>;
+               };
+       };
+};