[POWERPC] spufs: fix incorrect interrupt status clearing in backing mbox stat poll

When doing a poll on the mbox stat file of a swapped-out context, we
clear the class 0 interrupt status, rather than the class 2 interrupt
status.

This change corrects the poll operation to clear the correct interrupt.

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>

diff --git a/arch/powerpc/platforms/cell/spufs/backing_ops.c b/arch/powerpc/platforms/cell/spufs/backing_ops.c
index 15f915813710f22a3ab347b84d39a4b2d65cdb4d..97b2d5e587cca0cba7fa308ab680da79e3c462fc 100644 (file)
--- a/arch/powerpc/platforms/cell/spufs/backing_ops.c
+++ b/arch/powerpc/platforms/cell/spufs/backing_ops.c
@@ -106,7 +106,7 @@ static unsigned int spu_backing_mbox_stat_poll(struct spu_context *ctx,
                if (stat & 0xff0000)
                        ret |= POLLIN | POLLRDNORM;
                else {
-                       ctx->csa.priv1.int_stat_class0_RW &= ~0x1;
+                       ctx->csa.priv1.int_stat_class2_RW &= ~0x1;
                        ctx->csa.priv1.int_mask_class2_RW |= 0x1;
                }
        }
@@ -114,7 +114,7 @@ static unsigned int spu_backing_mbox_stat_poll(struct spu_context *ctx,
                if (stat & 0x00ff00)
                        ret = POLLOUT | POLLWRNORM;
                else {
-                       ctx->csa.priv1.int_stat_class0_RW &= ~0x10;
+                       ctx->csa.priv1.int_stat_class2_RW &= ~0x10;
                        ctx->csa.priv1.int_mask_class2_RW |= 0x10;
                }
        }