[MIPS] SMTC: Safety net for i8259A interrupts.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index c78d48349600872d87f721b8420f13d96cbe5e8b..97aeb8c4e6010aae5adbb86c8788f3f5e810f816 100644 (file)
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -330,6 +330,18 @@ void __init arch_init_irq(void)
                        (0x100 << MIPSCPU_INT_I8259A));
                setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
                        &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
+               /*
+                * Temporary hack to ensure that the subsidiary device
+                * interrupts coing in via the i8259A, but associated
+                * with low IRQ numbers, will restore the Status.IM
+                * value associated with the i8259A.
+                */
+               {
+                       int i;
+
+                       for (i = 0; i < 16; i++)
+                               irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
+               }
 #else /* Not SMTC */
                setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
                setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);