]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[ARM] nommu: add ARM740T core support
authorHyok S. Choi <hyok.choi@samsung.com>
Tue, 26 Sep 2006 08:37:50 +0000 (17:37 +0900)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 27 Sep 2006 16:39:17 +0000 (17:39 +0100)
This patch adds ARM740T core support which has a MPU and 4KB or 8KB cache.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/Makefile
arch/arm/mm/Kconfig
arch/arm/mm/Makefile
arch/arm/mm/proc-arm740.S [new file with mode: 0644]
include/asm-arm/cacheflush.h
include/asm-arm/proc-fns.h

index 282333fe0a742c5d8e92501e3f5b298ab86a6956..8ec4b46d2cbbe13d6b266ebe026f5e55e50b3116 100644 (file)
@@ -57,6 +57,7 @@ tune-$(CONFIG_CPU_ARM610)     :=-mtune=arm610
 tune-$(CONFIG_CPU_ARM710)      :=-mtune=arm710
 tune-$(CONFIG_CPU_ARM7TDMI)    :=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM720T)     :=-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM740T)     :=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM920T)     :=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM922T)     :=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM925T)     :=-mtune=arm9tdmi
index 9f860aa9c908c7a68bb4b37fd788468fc4fdf765..87f9fece960604635f1dd7f2a7837297bcf1af5b 100644 (file)
@@ -75,6 +75,21 @@ config CPU_ARM720T
          Say Y if you want support for the ARM720T processor.
          Otherwise, say N.
 
+# ARM740T
+config CPU_ARM740T
+       bool "Support ARM740T processor" if ARCH_INTEGRATOR
+       select CPU_32v4T
+       select CPU_ABRT_LV4T
+       select CPU_CACHE_V3     # although the core is v4t
+       select CPU_CP15_MPU
+       help
+         A 32-bit RISC processor with 8KB cache or 4KB variants,
+         write buffer and MPU(Protection Unit) built around
+         an ARM7TDMI core.
+
+         Say Y if you want support for the ARM740T processor.
+         Otherwise, say N.
+
 # ARM920T
 config CPU_ARM920T
        bool "Support ARM920T processor"
@@ -436,7 +451,7 @@ comment "Processor Features"
 
 config ARM_THUMB
        bool "Support Thumb user binaries"
-       depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
+       depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
        default y
        help
          Say Y if you want to include kernel support for running user space
@@ -473,7 +488,7 @@ config CPU_DCACHE_DISABLE
 
 config CPU_DCACHE_WRITETHROUGH
        bool "Force write through D-cache"
-       depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
+       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
        default y if CPU_ARM925T
        help
          Say Y here to use the data cache in writethrough mode. Unless you
index 908f6d437174631366b7e20e0d3c82e4ca5ed4df..d10db822d3b8aab20eb3e42e0b034c4528b234ea 100644 (file)
@@ -48,6 +48,7 @@ obj-$(CONFIG_CPU_ARM610)      += proc-arm6_7.o
 obj-$(CONFIG_CPU_ARM710)       += proc-arm6_7.o
 obj-$(CONFIG_CPU_ARM7TDMI)     += proc-arm7tdmi.o
 obj-$(CONFIG_CPU_ARM720T)      += proc-arm720.o
+obj-$(CONFIG_CPU_ARM740T)      += proc-arm740.o
 obj-$(CONFIG_CPU_ARM920T)      += proc-arm920.o
 obj-$(CONFIG_CPU_ARM922T)      += proc-arm922.o
 obj-$(CONFIG_CPU_ARM925T)      += proc-arm925.o
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
new file mode 100644 (file)
index 0000000..4071381
--- /dev/null
@@ -0,0 +1,174 @@
+/*
+ *  linux/arch/arm/mm/arm740.S: utility functions for ARM740
+ *
+ *  Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
+#include <asm/pgtable.h>
+#include <asm/procinfo.h>
+#include <asm/ptrace.h>
+
+       .text
+/*
+ * cpu_arm740_proc_init()
+ * cpu_arm740_do_idle()
+ * cpu_arm740_dcache_clean_area()
+ * cpu_arm740_switch_mm()
+ *
+ * These are not required.
+ */
+ENTRY(cpu_arm740_proc_init)
+ENTRY(cpu_arm740_do_idle)
+ENTRY(cpu_arm740_dcache_clean_area)
+ENTRY(cpu_arm740_switch_mm)
+       mov     pc, lr
+
+/*
+ * cpu_arm740_proc_fin()
+ */
+ENTRY(cpu_arm740_proc_fin)
+       stmfd   sp!, {lr}
+       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
+       msr     cpsr_c, ip
+       mrc     p15, 0, r0, c1, c0, 0
+       bic     r0, r0, #0x3f000000             @ bank/f/lock/s
+       bic     r0, r0, #0x0000000c             @ w-buffer/cache
+       mcr     p15, 0, r0, c1, c0, 0           @ disable caches
+       mcr     p15, 0, r0, c7, c0, 0           @ invalidate cache
+       ldmfd   sp!, {pc}
+
+/*
+ * cpu_arm740_reset(loc)
+ * Params  : r0 = address to jump to
+ * Notes   : This sets up everything for a reset
+ */
+ENTRY(cpu_arm740_reset)
+       mov     ip, #0
+       mcr     p15, 0, ip, c7, c0, 0           @ invalidate cache
+       mrc     p15, 0, ip, c1, c0, 0           @ get ctrl register
+       bic     ip, ip, #0x0000000c             @ ............wc..
+       mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
+       mov     pc, r0
+
+       __INIT
+
+       .type   __arm740_setup, #function
+__arm740_setup:
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c0, 0           @ invalidate caches
+
+       mcr     p15, 0, r0, c6, c3              @ disable area 3~7
+       mcr     p15, 0, r0, c6, c4
+       mcr     p15, 0, r0, c6, c5
+       mcr     p15, 0, r0, c6, c6
+       mcr     p15, 0, r0, c6, c7
+
+       mov     r0, #0x0000003F                 @ base = 0, size = 4GB
+       mcr     p15, 0, r0, c6, c0              @ set area 0, default
+
+       ldr     r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
+       ldr     r1, =(CONFIG_DRAM_SIZE >> 12)   @ size of RAM (must be >= 4KB)
+       mov     r2, #10                         @ 11 is the minimum (4KB)
+1:     add     r2, r2, #1                      @ area size *= 2
+       mov     r1, r1, lsr #1
+       bne     1b                              @ count not zero r-shift
+       orr     r0, r0, r2, lsl #1              @ the area register value
+       orr     r0, r0, #1                      @ set enable bit
+       mcr     p15, 0, r0, c6, c1              @ set area 1, RAM
+
+       ldr     r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
+       ldr     r1, =(CONFIG_FLASH_SIZE >> 12)  @ size of FLASH (must be >= 4KB)
+       mov     r2, #10                         @ 11 is the minimum (4KB)
+1:     add     r2, r2, #1                      @ area size *= 2
+       mov     r1, r1, lsr #1
+       bne     1b                              @ count not zero r-shift
+       orr     r0, r0, r2, lsl #1              @ the area register value
+       orr     r0, r0, #1                      @ set enable bit
+       mcr     p15, 0, r0, c6, c2              @ set area 2, ROM/FLASH
+
+       mov     r0, #0x06
+       mcr     p15, 0, r0, c2, c0              @ Region 1&2 cacheable
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+       mov     r0, #0x00                       @ disable whole write buffer
+#else
+       mov     r0, #0x02                       @ Region 1 write bufferred
+#endif
+       mcr     p15, 0, r0, c3, c0
+
+       mov     r0, #0x10000
+       sub     r0, r0, #1                      @ r0 = 0xffff
+       mcr     p15, 0, r0, c5, c0              @ all read/write access
+
+       mrc     p15, 0, r0, c1, c0              @ get control register
+       bic     r0, r0, #0x3F000000             @ set to standard caching mode
+                                               @ need some benchmark
+       orr     r0, r0, #0x0000000d             @ MPU/Cache/WB
+
+       mov     pc, lr
+
+       .size   __arm740_setup, . - __arm740_setup
+
+       __INITDATA
+
+/*
+ * Purpose : Function pointers used to access above functions - all calls
+ *          come through these
+ */
+       .type   arm740_processor_functions, #object
+ENTRY(arm740_processor_functions)
+       .word   v4t_late_abort
+       .word   cpu_arm740_proc_init
+       .word   cpu_arm740_proc_fin
+       .word   cpu_arm740_reset
+       .word   cpu_arm740_do_idle
+       .word   cpu_arm740_dcache_clean_area
+       .word   cpu_arm740_switch_mm
+       .word   0                       @ cpu_*_set_pte
+       .size   arm740_processor_functions, . - arm740_processor_functions
+
+       .section ".rodata"
+
+       .type   cpu_arch_name, #object
+cpu_arch_name:
+       .asciz  "armv4"
+       .size   cpu_arch_name, . - cpu_arch_name
+
+       .type   cpu_elf_name, #object
+cpu_elf_name:
+       .asciz  "v4"
+       .size   cpu_elf_name, . - cpu_elf_name
+
+       .type   cpu_arm740_name, #object
+cpu_arm740_name:
+       .ascii  "ARM740T"
+       .size   cpu_arm740_name, . - cpu_arm740_name
+
+       .align
+
+       .section ".proc.info.init", #alloc, #execinstr
+       .type   __arm740_proc_info,#object
+__arm740_proc_info:
+       .long   0x41807400
+       .long   0xfffffff0
+       .long   0
+       b       __arm740_setup
+       .long   cpu_arch_name
+       .long   cpu_elf_name
+       .long   HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
+       .long   cpu_arm740_name
+       .long   arm740_processor_functions
+       .long   0
+       .long   0
+       .long   v3_cache_fns                    @ cache model
+       .size   __arm740_proc_info, . - __arm740_proc_info
+
+
index e7bfff298e464a4ef908c70b96d7fea4f7d40c84..24924e64f883933ee8f2ddef8d555eac42b44a64 100644 (file)
@@ -25,7 +25,8 @@
 #undef _CACHE
 #undef MULTI_CACHE
 
-#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
+#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) || \
+    defined(CONFIG_CPU_ARM740T)
 # ifdef _CACHE
 #  define MULTI_CACHE 1
 # else
index 3e8c057e66b5f3bdd60b3a899c2e92bf380edeca..17dfc0de965822d905fff44a11e18bc15bbdea2a 100644 (file)
 #   define CPU_NAME cpu_arm720
 #  endif
 # endif
+# ifdef CONFIG_CPU_ARM740T
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm740
+#  endif
+# endif
 # ifdef CONFIG_CPU_ARM920T
 #  ifdef CPU_NAME
 #   undef  MULTI_CPU