#define INT_24XX_USB_IRQ_HGEN 78
#define INT_24XX_USB_IRQ_HSOF 79
#define INT_24XX_USB_IRQ_OTG 80
+ #define INT_24XX_MCBSP5_IRQ_TX 81
+ #define INT_24XX_MCBSP5_IRQ_RX 82
#define INT_24XX_MMC_IRQ 83
+ #define INT_24XX_MMC2_IRQ 86
+ #define INT_24XX_MCBSP3_IRQ_TX 89
+ #define INT_24XX_MCBSP3_IRQ_RX 90
+ #define INT_24XX_SPI3_IRQ 91
+
+ #define INT_243X_MCBSP2_IRQ 16
+ #define INT_243X_MCBSP3_IRQ 17
+ #define INT_243X_MCBSP4_IRQ 18
+ #define INT_243X_MCBSP5_IRQ 19
+ #define INT_243X_MCBSP1_IRQ 64
+ #define INT_243X_HS_USB_MC 92
+ #define INT_243X_HS_USB_DMA 93
+ #define INT_243X_CARKIT_IRQ 94
+
+ #define INT_34XX_BENCH_MPU_EMUL 3
+ #define INT_34XX_ST_MCBSP2_IRQ 4
+ #define INT_34XX_ST_MCBSP3_IRQ 5
+ #define INT_34XX_SSM_ABORT_IRQ 6
+ #define INT_34XX_SYS_NIRQ 7
+ #define INT_34XX_D2D_FW_IRQ 8
+ #define INT_34XX_PRCM_MPU_IRQ 11
+ #define INT_34XX_MCBSP1_IRQ 16
+ #define INT_34XX_MCBSP2_IRQ 17
+ #define INT_34XX_MCBSP3_IRQ 22
+ #define INT_34XX_MCBSP4_IRQ 23
+ #define INT_34XX_CAM_IRQ 24
+ #define INT_34XX_MCBSP5_IRQ 27
+ #define INT_34XX_GPIO_BANK1 29
+ #define INT_34XX_GPIO_BANK2 30
+ #define INT_34XX_GPIO_BANK3 31
+ #define INT_34XX_GPIO_BANK4 32
+ #define INT_34XX_GPIO_BANK5 33
+ #define INT_34XX_GPIO_BANK6 34
+ #define INT_34XX_USIM_IRQ 35
+ #define INT_34XX_WDT3_IRQ 36
+ #define INT_34XX_SPI4_IRQ 48
+ #define INT_34XX_SHA1MD52_IRQ 49
+ #define INT_34XX_FPKA_READY_IRQ 50
+ #define INT_34XX_SHA1MD51_IRQ 51
+ #define INT_34XX_RNG_IRQ 52
+ #define INT_34XX_I2C3_IRQ 61
+ #define INT_34XX_FPKA_ERROR_IRQ 64
+ #define INT_34XX_PBIAS_IRQ 75
+ #define INT_34XX_OHCI_IRQ 76
+ #define INT_34XX_EHCI_IRQ 77
+ #define INT_34XX_TLL_IRQ 78
+ #define INT_34XX_PARTHASH_IRQ 79
+ #define INT_34XX_MMC3_IRQ 94
+ #define INT_34XX_GPT12_IRQ 95
+#define INT_34XX_BENCH_MPU_EMUL 3
+
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
* 16 MPUIO lines */
#define OMAP_MAX_GPIO_LINES 192