i915: GM45 has GM965-style MCH setup.

Fixes tiling swizzling mode failures that manifest in glReadPixels().

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 6b3f1e4a34a1939a42e67f3298d47d8fb26c66cc..e8b85ac4ca041159553f5211e0bc3cbe58f03cc8 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -96,7 +96,8 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
                 */
                swizzle_x = I915_BIT_6_SWIZZLE_NONE;
                swizzle_y = I915_BIT_6_SWIZZLE_NONE;
-       } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) {
+       } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev) ||
+                  IS_GM45(dev)) {
                uint32_t dcc;
 
                /* On 915-945 and GM965, channel interleave by the CPU is
@@ -118,7 +119,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
                            dcc & DCC_CHANNEL_XOR_DISABLE) {
                                swizzle_x = I915_BIT_6_SWIZZLE_9_10;
                                swizzle_y = I915_BIT_6_SWIZZLE_9;
-                       } else if (IS_I965GM(dev)) {
+                       } else if (IS_I965GM(dev) || IS_GM45(dev)) {
                                /* GM965 only does bit 11-based channel
                                 * randomization
                                 */