{
void __iomem *mbase = musb->mregs;
int handled = 1;
- u8 bResult[2], bEnd = 0;
+ u8 bResult[2], epnum = 0;
const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
bResult[1] = 0;
u16 tmp;
void __iomem *regs;
- bEnd = (u8) pControlRequest->wIndex;
- if (!bEnd) {
+ epnum = (u8) pControlRequest->wIndex;
+ if (!epnum) {
bResult[0] = 0;
break;
}
- is_in = bEnd & USB_DIR_IN;
+ is_in = epnum & USB_DIR_IN;
if (is_in) {
- bEnd &= 0x0f;
- ep = &musb->endpoints[bEnd].ep_in;
+ epnum &= 0x0f;
+ ep = &musb->endpoints[epnum].ep_in;
} else {
- ep = &musb->endpoints[bEnd].ep_out;
+ ep = &musb->endpoints[epnum].ep_out;
}
- regs = musb->endpoints[bEnd].regs;
+ regs = musb->endpoints[epnum].regs;
- if (bEnd >= MUSB_C_NUM_EPS || !ep->desc) {
+ if (epnum >= MUSB_C_NUM_EPS || !ep->desc) {
handled = -EINVAL;
break;
}
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
if (is_in)
tmp = musb_readw(regs, MGC_O_HDRC_TXCSR)
& MGC_M_TXCSR_P_SENDSTALL;
case USB_RECIP_INTERFACE:
break;
case USB_RECIP_ENDPOINT:{
- const u8 bEnd = pControlRequest->wIndex & 0x0f;
+ const u8 epnum = pControlRequest->wIndex & 0x0f;
struct musb_ep *musb_ep;
- if (bEnd == 0
- || bEnd >= MUSB_C_NUM_EPS
+ if (epnum == 0
+ || epnum >= MUSB_C_NUM_EPS
|| pControlRequest->wValue
!= USB_ENDPOINT_HALT)
break;
if (pControlRequest->wIndex & USB_DIR_IN)
- musb_ep = &musb->endpoints[bEnd].ep_in;
+ musb_ep = &musb->endpoints[epnum].ep_in;
else
- musb_ep = &musb->endpoints[bEnd].ep_out;
+ musb_ep = &musb->endpoints[epnum].ep_out;
if (!musb_ep->desc)
break;
break;
case USB_RECIP_ENDPOINT:{
- const u8 bEnd =
+ const u8 epnum =
pControlRequest->wIndex & 0x0f;
struct musb_ep *musb_ep;
struct musb_hw_ep *ep;
int is_in;
u16 csr;
- if (bEnd == 0
- || bEnd >= MUSB_C_NUM_EPS
+ if (epnum == 0
+ || epnum >= MUSB_C_NUM_EPS
|| pControlRequest->wValue
!= USB_ENDPOINT_HALT)
break;
- ep = musb->endpoints + bEnd;
+ ep = musb->endpoints + epnum;
regs = ep->regs;
is_in = pControlRequest->wIndex & USB_DIR_IN;
if (is_in)
if (!musb_ep->desc)
break;
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
if (is_in) {
csr = musb_readw(regs,
MGC_O_HDRC_TXCSR);
*/
static void txstate(struct musb *musb, struct musb_request *req)
{
- u8 bEnd = req->bEnd;
+ u8 epnum = req->epnum;
struct musb_ep *musb_ep;
- void __iomem *epio = musb->endpoints[bEnd].regs;
+ void __iomem *epio = musb->endpoints[epnum].regs;
struct usb_request *pRequest;
u16 fifo_count = 0, wCsrVal;
int use_dma = 0;
}
DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
- bEnd, musb_ep->wPacketSize, fifo_count,
+ epnum, musb_ep->wPacketSize, fifo_count,
wCsrVal);
#ifndef CONFIG_USB_INVENTRA_FIFO
* FIFO state update (e.g. data ready).
* Called from IRQ, with controller locked.
*/
-void musb_g_tx(struct musb *musb, u8 bEnd)
+void musb_g_tx(struct musb *musb, u8 epnum)
{
u16 wCsrVal;
struct usb_request *pRequest;
u8 __iomem *mbase = musb->mregs;
- struct musb_ep *musb_ep = &musb->endpoints[bEnd].ep_in;
- void __iomem *epio = musb->endpoints[bEnd].regs;
+ struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
+ void __iomem *epio = musb->endpoints[epnum].regs;
struct dma_channel *dma;
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
pRequest = next_request(musb_ep);
wCsrVal = musb_readw(epio, MGC_O_HDRC_TXCSR);
wCsrVal &= ~(MGC_M_TXCSR_P_UNDERRUN
| MGC_M_TXCSR_TXPKTRDY);
musb_writew(epio, MGC_O_HDRC_TXCSR, wCsrVal);
- DBG(20, "underrun on ep%d, req %p\n", bEnd, pRequest);
+ DBG(20, "underrun on ep%d, req %p\n", epnum, pRequest);
}
if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
pRequest->actual += musb_ep->dma->dwActualLength;
DBG(4, "TXCSR%d %04x, dma off, "
"len %Zd, req %p\n",
- bEnd, wCsrVal,
+ epnum, wCsrVal,
musb_ep->dma->dwActualLength,
pRequest);
}
* REVISIT for double buffering...
* FIXME revisit for stalls too...
*/
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
wCsrVal = musb_readw(epio, MGC_O_HDRC_TXCSR);
if (wCsrVal & MGC_M_TXCSR_FIFONOTEMPTY)
break;
static void rxstate(struct musb *musb, struct musb_request *req)
{
u16 wCsrVal = 0;
- const u8 bEnd = req->bEnd;
+ const u8 epnum = req->epnum;
struct usb_request *pRequest = &req->request;
- struct musb_ep *musb_ep = &musb->endpoints[bEnd].ep_out;
- void __iomem *epio = musb->endpoints[bEnd].regs;
+ struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
+ void __iomem *epio = musb->endpoints[epnum].regs;
u16 fifo_count = 0;
u16 len = musb_ep->wPacketSize;
/*
* Data ready for a request; called from IRQ
*/
-void musb_g_rx(struct musb *musb, u8 bEnd)
+void musb_g_rx(struct musb *musb, u8 epnum)
{
u16 wCsrVal;
struct usb_request *pRequest;
void __iomem *mbase = musb->mregs;
- struct musb_ep *musb_ep = &musb->endpoints[bEnd].ep_out;
- void __iomem *epio = musb->endpoints[bEnd].regs;
+ struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
+ void __iomem *epio = musb->endpoints[epnum].regs;
struct dma_channel *dma;
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
pRequest = next_request(musb_ep);
pRequest->actual += musb_ep->dma->dwActualLength;
DBG(4, "RXCSR%d %04x, dma off, %04x, len %Zd, req %p\n",
- bEnd, wCsrVal,
+ epnum, wCsrVal,
musb_readw(epio, MGC_O_HDRC_RXCSR),
musb_ep->dma->dwActualLength, pRequest);
goto done;
/* don't start more i/o till the stall clears */
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
wCsrVal = musb_readw(epio, MGC_O_HDRC_RXCSR);
if (wCsrVal & MGC_M_RXCSR_P_SENDSTALL)
goto done;
void __iomem *regs;
struct musb *musb;
void __iomem *mbase;
- u8 bEnd;
+ u8 epnum;
u16 csr;
unsigned tmp;
int status = -EINVAL;
regs = hw_ep->regs;
musb = musb_ep->musb;
mbase = musb->mregs;
- bEnd = musb_ep->current_epnum;
+ epnum = musb_ep->current_epnum;
spin_lock_irqsave(&musb->Lock, flags);
musb_ep->type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
/* check direction and (later) maxpacket size against endpoint */
- if ((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != bEnd)
+ if ((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != epnum)
goto fail;
/* REVISIT this rules out high bandwidth periodic transfers */
/* enable the interrupts for the endpoint, set the endpoint
* packet size (or fail), set the mode, clear the fifo
*/
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
if (desc->bEndpointAddress & USB_DIR_IN) {
u16 wIntrTxE = musb_readw(mbase, MGC_O_HDRC_INTRTXE);
if (tmp > hw_ep->wMaxPacketSizeTx)
goto fail;
- wIntrTxE |= (1 << bEnd);
+ wIntrTxE |= (1 << epnum);
musb_writew(mbase, MGC_O_HDRC_INTRTXE, wIntrTxE);
/* REVISIT if can_bulk_split(), use by updating "tmp";
if (tmp > hw_ep->wMaxPacketSizeRx)
goto fail;
- wIntrRxE |= (1 << bEnd);
+ wIntrRxE |= (1 << epnum);
musb_writew(mbase, MGC_O_HDRC_INTRRXE, wIntrRxE);
/* REVISIT if can_bulk_combine() use by updating "tmp"
{
unsigned long flags;
struct musb *musb;
- u8 bEnd;
+ u8 epnum;
struct musb_ep *musb_ep;
void __iomem *epio;
int status = 0;
musb_ep = to_musb_ep(ep);
musb = musb_ep->musb;
- bEnd = musb_ep->current_epnum;
- epio = musb->endpoints[bEnd].regs;
+ epnum = musb_ep->current_epnum;
+ epio = musb->endpoints[epnum].regs;
spin_lock_irqsave(&musb->Lock, flags);
- MGC_SelectEnd(musb->mregs, bEnd);
+ MGC_SelectEnd(musb->mregs, epnum);
/* zero the endpoint sizes */
if (musb_ep->is_in) {
u16 wIntrTxE = musb_readw(musb->mregs, MGC_O_HDRC_INTRTXE);
- wIntrTxE &= ~(1 << bEnd);
+ wIntrTxE &= ~(1 << epnum);
musb_writew(musb->mregs, MGC_O_HDRC_INTRTXE, wIntrTxE);
musb_writew(epio, MGC_O_HDRC_TXMAXP, 0);
} else {
u16 wIntrRxE = musb_readw(musb->mregs, MGC_O_HDRC_INTRRXE);
- wIntrRxE &= ~(1 << bEnd);
+ wIntrRxE &= ~(1 << epnum);
musb_writew(musb->mregs, MGC_O_HDRC_INTRRXE, wIntrRxE);
musb_writew(epio, MGC_O_HDRC_RXMAXP, 0);
}
if (pRequest) {
INIT_LIST_HEAD(&pRequest->request.list);
pRequest->request.dma = DMA_ADDR_INVALID;
- pRequest->bEnd = musb_ep->current_epnum;
+ pRequest->epnum = musb_ep->current_epnum;
pRequest->ep = musb_ep;
}
{
DBG(3, "<== %s request %p len %u on hw_ep%d\n",
req->bTx ? "TX/IN" : "RX/OUT",
- &req->request, req->request.length, req->bEnd);
+ &req->request, req->request.length, req->epnum);
- MGC_SelectEnd(musb->mregs, req->bEnd);
+ MGC_SelectEnd(musb->mregs, req->epnum);
if (req->bTx)
txstate(musb, req);
else
/* request is mine now... */
pRequest->request.actual = 0;
pRequest->request.status = -EINPROGRESS;
- pRequest->bEnd = musb_ep->current_epnum;
+ pRequest->epnum = musb_ep->current_epnum;
pRequest->bTx = musb_ep->is_in;
if (is_dma_capable() && musb_ep->dma) {
int musb_gadget_set_halt(struct usb_ep *ep, int value)
{
struct musb_ep *musb_ep = to_musb_ep(ep);
- u8 bEnd = musb_ep->current_epnum;
+ u8 epnum = musb_ep->current_epnum;
struct musb *musb = musb_ep->musb;
- void __iomem *epio = musb->endpoints[bEnd].regs;
+ void __iomem *epio = musb->endpoints[epnum].regs;
void __iomem *mbase;
unsigned long flags;
u16 wCsr;
goto done;
}
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
/* cannot portably stall with non-empty FIFO */
pRequest = to_musb_request(next_request(musb_ep));
if (musb_ep->desc && !musb_ep->is_in) {
struct musb *musb = musb_ep->musb;
- int bEnd = musb_ep->current_epnum;
+ int epnum = musb_ep->current_epnum;
void __iomem *mbase = musb->mregs;
unsigned long flags;
spin_lock_irqsave(&musb->Lock, flags);
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
/* FIXME return zero unless RXPKTRDY is set */
retval = musb_readw(epio, MGC_O_HDRC_RXCOUNT);
static void __init
-init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 bEnd, int is_in)
+init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
{
- struct musb_hw_ep *hw_ep = musb->endpoints + bEnd;
+ struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
memset(ep, 0, sizeof *ep);
- ep->current_epnum = bEnd;
+ ep->current_epnum = epnum;
ep->musb = musb;
ep->hw_ep = hw_ep;
ep->is_in = is_in;
INIT_LIST_HEAD(&ep->req_list);
- sprintf(ep->name, "ep%d%s", bEnd,
- (!bEnd || hw_ep->bIsSharedFifo) ? "" : (
+ sprintf(ep->name, "ep%d%s", epnum,
+ (!epnum || hw_ep->bIsSharedFifo) ? "" : (
is_in ? "in" : "out"));
ep->end_point.name = ep->name;
INIT_LIST_HEAD(&ep->end_point.ep_list);
- if (!bEnd) {
+ if (!epnum) {
ep->end_point.maxpacket = 64;
ep->end_point.ops = &musb_g_ep0_ops;
musb->g.ep0 = &ep->end_point;
*/
static inline void __init musb_g_init_endpoints(struct musb *musb)
{
- u8 bEnd;
+ u8 epnum;
struct musb_hw_ep *hw_ep;
unsigned count = 0;
/* intialize endpoint list just once */
INIT_LIST_HEAD(&(musb->g.ep_list));
- for (bEnd = 0, hw_ep = musb->endpoints;
- bEnd < musb->nr_endpoints;
- bEnd++, hw_ep++) {
- if (hw_ep->bIsSharedFifo /* || !bEnd */) {
- init_peripheral_ep(musb, &hw_ep->ep_in, bEnd, 0);
+ for (epnum = 0, hw_ep = musb->endpoints;
+ epnum < musb->nr_endpoints;
+ epnum++, hw_ep++) {
+ if (hw_ep->bIsSharedFifo /* || !epnum */) {
+ init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
count++;
} else {
if (hw_ep->wMaxPacketSizeTx) {
init_peripheral_ep(musb, &hw_ep->ep_in,
- bEnd, 1);
+ epnum, 1);
count++;
}
if (hw_ep->wMaxPacketSizeRx) {
init_peripheral_ep(musb, &hw_ep->ep_out,
- bEnd, 0);
+ epnum, 0);
count++;
}
}
i < musb->nr_endpoints;
i++, hw_ep++) {
MGC_SelectEnd(musb->mregs, i);
- if (hw_ep->bIsSharedFifo /* || !bEnd */) {
+ if (hw_ep->bIsSharedFifo /* || !epnum */) {
nuke(&hw_ep->ep_in, -ESHUTDOWN);
} else {
if (hw_ep->wMaxPacketSizeTx)
struct musb_ep *ep;
struct musb *musb;
u8 bTx; /* endpoint direction */
- u8 bEnd;
+ u8 epnum;
u8 mapped;
};
return container_of(queue->next, struct usb_request, list);
}
-extern void musb_g_tx(struct musb *musb, u8 bEnd);
-extern void musb_g_rx(struct musb *musb, u8 bEnd);
+extern void musb_g_tx(struct musb *musb, u8 epnum);
+extern void musb_g_rx(struct musb *musb, u8 epnum);
extern const struct usb_ep_ops musb_g_ep0_ops;
/*************************** Forwards ***************************/
-static void musb_ep_program(struct musb *musb, u8 bEnd,
+static void musb_ep_program(struct musb *musb, u8 epnum,
struct urb *pUrb, unsigned int nOut,
u8 * pBuffer, u32 dwLength);
struct musb_hw_ep *hw_ep = qh->hw_ep;
unsigned nPipe = urb->pipe;
u8 bAddress = usb_pipedevice(nPipe);
- int bEnd = hw_ep->epnum;
+ int epnum = hw_ep->epnum;
/* initialize software qh state */
qh->offset = 0;
case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
default: s = "-intr"; break;
}; s;}),
- bEnd, pBuffer, dwLength);
+ epnum, pBuffer, dwLength);
/* Configure endpoint */
if (is_in || hw_ep->bIsSharedFifo)
hw_ep->in_qh = qh;
else
hw_ep->out_qh = qh;
- musb_ep_program(musb, bEnd, urb, !is_in, pBuffer, dwLength);
+ musb_ep_program(musb, epnum, urb, !is_in, pBuffer, dwLength);
/* transmit may have more work: start it when it is time */
if (is_in)
} else {
qh->frame = urb->start_frame;
/* enable SOF interrupt so we can count down */
-DBG(1,"SOF for %d\n", bEnd);
+DBG(1,"SOF for %d\n", epnum);
#if 1 // ifndef CONFIG_ARCH_DAVINCI
musb_writeb(mbase, MGC_O_HDRC_INTRUSBE, 0xff);
#endif
break;
default:
start:
- DBG(4, "Start TX%d %s\n", bEnd,
+ DBG(4, "Start TX%d %s\n", epnum,
hw_ep->tx_channel ? "dma" : "pio");
if (!hw_ep->tx_channel)
* PIO RX for a packet (or part of it).
*/
static u8 musb_host_packet_rx(struct musb *musb, struct urb *pUrb,
- u8 bEnd, u8 bIsochError)
+ u8 epnum, u8 bIsochError)
{
u16 wRxCount;
u8 *pBuffer;
u8 bDone = FALSE;
u32 length;
int do_flush = 0;
- struct musb_hw_ep *hw_ep = musb->endpoints + bEnd;
+ struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
void __iomem *epio = hw_ep->regs;
struct musb_qh *qh = hw_ep->in_qh;
int nPipe = pUrb->pipe;
void *buffer = pUrb->transfer_buffer;
- // MGC_SelectEnd(mbase, bEnd);
+ // MGC_SelectEnd(mbase, epnum);
wRxCount = musb_readw(epio, MGC_O_HDRC_RXCOUNT);
- DBG(3, "RX%d count %d, buffer %p len %d/%d\n", bEnd, wRxCount,
+ DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, wRxCount,
pUrb->transfer_buffer, qh->offset,
pUrb->transfer_buffer_length);
* Program an HDRC endpoint as per the given URB
* Context: irqs blocked, controller lock held
*/
-static void musb_ep_program(struct musb *musb, u8 bEnd,
+static void musb_ep_program(struct musb *musb, u8 epnum,
struct urb *pUrb, unsigned int is_out,
u8 * pBuffer, u32 dwLength)
{
struct dma_channel *pDmaChannel;
u8 bDmaOk;
void __iomem *mbase = musb->mregs;
- struct musb_hw_ep *hw_ep = musb->endpoints + bEnd;
+ struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
void __iomem *epio = hw_ep->regs;
struct musb_qh *qh;
u16 wPacketSize;
DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
"h_addr%02x h_port%02x bytes %d\n",
is_out ? "-->" : "<--",
- bEnd, pUrb, pUrb->dev->speed,
+ epnum, pUrb, pUrb->dev->speed,
qh->addr_reg, qh->epnum, is_out ? "out" : "in",
qh->h_addr_reg, qh->h_port_reg,
dwLength);
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
/* candidate for DMA? */
pDmaController = musb->pDmaController;
- if (is_dma_capable() && bEnd && pDmaController) {
+ if (is_dma_capable() && epnum && pDmaController) {
pDmaChannel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
if (!pDmaChannel) {
pDmaChannel = pDmaController->channel_alloc(
/* disable interrupt in case we flush */
wIntrTxE = musb_readw(mbase, MGC_O_HDRC_INTRTXE);
- musb_writew(mbase, MGC_O_HDRC_INTRTXE, wIntrTxE & ~(1 << bEnd));
+ musb_writew(mbase, MGC_O_HDRC_INTRTXE, wIntrTxE & ~(1 << epnum));
/* general endpoint setup */
- if (bEnd) {
+ if (epnum) {
u16 csr = wCsr;
/* ASSERT: TXCSR_DMAENAB was already cleared */
/* target addr and (for multipoint) hub addr/port */
if (musb->bIsMultipoint) {
musb_writeb(mbase,
- MGC_BUSCTL_OFFSET(bEnd, MGC_O_HDRC_TXFUNCADDR),
+ MGC_BUSCTL_OFFSET(epnum, MGC_O_HDRC_TXFUNCADDR),
qh->addr_reg);
musb_writeb(mbase,
- MGC_BUSCTL_OFFSET(bEnd, MGC_O_HDRC_TXHUBADDR),
+ MGC_BUSCTL_OFFSET(epnum, MGC_O_HDRC_TXHUBADDR),
qh->h_addr_reg);
musb_writeb(mbase,
- MGC_BUSCTL_OFFSET(bEnd, MGC_O_HDRC_TXHUBPORT),
+ MGC_BUSCTL_OFFSET(epnum, MGC_O_HDRC_TXHUBPORT),
qh->h_port_reg);
-/* FIXME if !bEnd, do the same for RX ... */
+/* FIXME if !epnum, do the same for RX ... */
} else
musb_writeb(mbase, MGC_O_HDRC_FADDR, qh->addr_reg);
/* protocol/endpoint/interval/NAKlimit */
- if (bEnd) {
+ if (epnum) {
musb_writeb(epio, MGC_O_HDRC_TXTYPE, qh->type_reg);
if (can_bulk_split(musb, qh->type))
musb_writew(epio, MGC_O_HDRC_TXMAXP,
/* write CSR */
wCsr |= MGC_M_TXCSR_MODE;
- if (bEnd)
+ if (epnum)
musb_writew(epio, MGC_O_HDRC_TXCSR, wCsr);
}
}
csr |= MGC_M_RXCSR_H_REQPKT;
- DBG(7, "RXCSR%d := %04x\n", bEnd, csr);
+ DBG(7, "RXCSR%d := %04x\n", epnum, csr);
musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR, csr);
csr = musb_readw(hw_ep->regs, MGC_O_HDRC_RXCSR);
}
#endif
/* Service a Tx-Available or dma completion irq for the endpoint */
-void musb_host_tx(struct musb *musb, u8 bEnd)
+void musb_host_tx(struct musb *musb, u8 epnum)
{
int nPipe;
u8 bDone = FALSE;
size_t wLength = 0;
u8 *pBuffer = NULL;
struct urb *pUrb;
- struct musb_hw_ep *hw_ep = musb->endpoints + bEnd;
+ struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
void __iomem *epio = hw_ep->regs;
struct musb_qh *qh = hw_ep->out_qh;
u32 status = 0;
pUrb = next_urb(qh);
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
wTxCsrVal = musb_readw(epio, MGC_O_HDRC_TXCSR);
/* with CPPI, DMA sometimes triggers "extra" irqs */
if (!pUrb) {
- DBG(4, "extra TX%d ready, csr %04x\n", bEnd, wTxCsrVal);
+ DBG(4, "extra TX%d ready, csr %04x\n", epnum, wTxCsrVal);
goto finish;
}
nPipe = pUrb->pipe;
dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
- DBG(4, "OUT/TX%d end, csr %04x%s\n", bEnd, wTxCsrVal,
+ DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, wTxCsrVal,
dma ? ", dma" : "");
/* check for errors */
if (wTxCsrVal & MGC_M_TXCSR_H_RXSTALL) {
/* dma was disabled, fifo flushed */
- DBG(3, "TX end %d stall\n", bEnd);
+ DBG(3, "TX end %d stall\n", epnum);
/* stall; record URB status */
status = -EPIPE;
} else if (wTxCsrVal & MGC_M_TXCSR_H_ERROR) {
/* (NON-ISO) dma was disabled, fifo flushed */
- DBG(3, "TX 3strikes on ep=%d\n", bEnd);
+ DBG(3, "TX 3strikes on ep=%d\n", epnum);
status = -ETIMEDOUT;
} else if (wTxCsrVal & MGC_M_TXCSR_H_NAKTIMEOUT) {
- DBG(6, "TX end=%d device not responding\n", bEnd);
+ DBG(6, "TX end=%d device not responding\n", epnum);
/* NOTE: this code path would be a good place to PAUSE a
* transfer, if there's some other (nonperiodic) tx urb
* if (bulk && qh->ring.next != &musb->out_bulk), then
* we have a candidate... NAKing is *NOT* an error
*/
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
musb_writew(epio, MGC_O_HDRC_CSR0,
MGC_M_TXCSR_H_WZC_BITS
| MGC_M_TXCSR_TXPKTRDY);
| MGC_M_TXCSR_H_NAKTIMEOUT
);
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
musb_writew(epio, MGC_O_HDRC_TXCSR, wTxCsrVal);
/* REVISIT may need to clear FLUSHFIFO ... */
musb_writew(epio, MGC_O_HDRC_TXCSR, wTxCsrVal);
/* second cppi case */
if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
- DBG(4, "extra TX%d ready, csr %04x\n", bEnd, wTxCsrVal);
+ DBG(4, "extra TX%d ready, csr %04x\n", epnum, wTxCsrVal);
goto finish;
}
musb_write_fifo(hw_ep, wLength, pBuffer);
qh->segsize = wLength;
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
musb_writew(epio, MGC_O_HDRC_TXCSR,
MGC_M_TXCSR_H_WZC_BITS | MGC_M_TXCSR_TXPKTRDY);
} else
* Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
* and high-bandwidth IN transfer cases.
*/
-void musb_host_rx(struct musb *musb, u8 bEnd)
+void musb_host_rx(struct musb *musb, u8 epnum)
{
struct urb *pUrb;
- struct musb_hw_ep *hw_ep = musb->endpoints + bEnd;
+ struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
void __iomem *epio = hw_ep->regs;
struct musb_qh *qh = hw_ep->in_qh;
size_t xfer_len;
u32 status;
struct dma_channel *dma;
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
pUrb = next_urb(qh);
dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
* usbtest #11 (unlinks) triggers it regularly, sometimes
* with fifo full. (Only with DMA??)
*/
- DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", bEnd, wVal,
+ DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, wVal,
musb_readw(epio, MGC_O_HDRC_RXCOUNT));
musb_h_flush_rxfifo(hw_ep, MGC_M_RXCSR_CLRDATATOG);
return;
nPipe = pUrb->pipe;
DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zd)\n",
- bEnd, wRxCsrVal, pUrb->actual_length,
+ epnum, wRxCsrVal, pUrb->actual_length,
dma ? dma->dwActualLength : 0);
/* check for errors, concurrent stall & unlink is not really
* handled yet! */
if (wRxCsrVal & MGC_M_RXCSR_H_RXSTALL) {
- DBG(3, "RX end %d STALL\n", bEnd);
+ DBG(3, "RX end %d STALL\n", epnum);
/* stall; record URB status */
status = -EPIPE;
} else if (wRxCsrVal & MGC_M_RXCSR_H_ERROR) {
- DBG(3, "end %d RX proto error\n", bEnd);
+ DBG(3, "end %d RX proto error\n", epnum);
status = -EPROTO;
musb_writeb(epio, MGC_O_HDRC_RXINTERVAL, 0);
* if (bulk && qh->ring.next != &musb->in_bulk), then
* we have a candidate... NAKing is *NOT* an error
*/
- DBG(6, "RX end %d NAK timeout\n", bEnd);
- MGC_SelectEnd(mbase, bEnd);
+ DBG(6, "RX end %d NAK timeout\n", epnum);
+ MGC_SelectEnd(mbase, epnum);
musb_writew(epio, MGC_O_HDRC_RXCSR,
MGC_M_RXCSR_H_WZC_BITS
| MGC_M_RXCSR_H_REQPKT);
goto finish;
} else {
- DBG(4, "RX end %d ISO data error\n", bEnd);
+ DBG(4, "RX end %d ISO data error\n", epnum);
/* packet error reported later */
bIsochError = TRUE;
}
if (unlikely(dma_channel_status(dma) == MGC_DMA_STATUS_BUSY)) {
/* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
- ERR("RX%d dma busy, csr %04x\n", bEnd, wRxCsrVal);
+ ERR("RX%d dma busy, csr %04x\n", epnum, wRxCsrVal);
goto finish;
}
bDone = TRUE;
}
- DBG(2, "RXCSR%d %04x, reqpkt, len %zd%s\n", bEnd, wRxCsrVal,
+ DBG(2, "RXCSR%d %04x, reqpkt, len %zd%s\n", epnum, wRxCsrVal,
xfer_len, dma ? ", dma" : "");
wRxCsrVal &= ~MGC_M_RXCSR_H_REQPKT;
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
musb_writew(epio, MGC_O_HDRC_RXCSR,
MGC_M_RXCSR_H_WZC_BITS | wRxCsrVal);
}
MGC_M_RXCSR_H_WZC_BITS | wVal);
}
- DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", bEnd,
+ DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
bDone ? "off" : "reset",
musb_readw(epio, MGC_O_HDRC_RXCSR),
musb_readw(epio, MGC_O_HDRC_RXCOUNT));
// SCRUB (RX)
/* do the proper sequence to abort the transfer */
- MGC_SelectEnd(mbase, bEnd);
+ MGC_SelectEnd(mbase, epnum);
wVal &= ~MGC_M_RXCSR_H_REQPKT;
musb_writew(epio, MGC_O_HDRC_RXCSR, wVal);
goto finish;
wRxCount = musb_readw(epio, MGC_O_HDRC_RXCOUNT);
DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
- bEnd, wRxCount,
+ epnum, wRxCount,
pUrb->transfer_dma
+ pUrb->actual_length,
qh->offset,
if (!dma) {
bDone = musb_host_packet_rx(musb, pUrb,
- bEnd, bIsochError);
+ epnum, bIsochError);
DBG(6, "read %spacket\n", bDone ? "last " : "");
}
}
#endif
static int
-dump_end_info(struct musb *musb, u8 bEnd, char *aBuffer, unsigned max)
+dump_end_info(struct musb *musb, u8 epnum, char *aBuffer, unsigned max)
{
int code = 0;
char *buf = aBuffer;
- struct musb_hw_ep *hw_ep = &musb->endpoints[bEnd];
+ struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
do {
- MGC_SelectEnd(musb->mregs, bEnd);
+ MGC_SelectEnd(musb->mregs, epnum);
#ifdef CONFIG_USB_MUSB_HDRC_HCD
if (is_host_active(musb)) {
int dump_rx, dump_tx;
/* TEMPORARY (!) until we have a real periodic
* schedule tree ...
*/
- if (!bEnd) {
+ if (!epnum) {
/* control is shared, uses RX queue
* but (mostly) shadowed tx registers
*/
} else if (hw_ep == musb->bulk_ep) {
dump_tx = !list_empty(&musb->out_bulk);
dump_rx = !list_empty(&musb->in_bulk);
- } else if (musb->periodic[bEnd]) {
+ } else if (musb->periodic[epnum]) {
struct usb_host_endpoint *hep;
- hep = musb->periodic[bEnd]->hep;
+ hep = musb->periodic[epnum]->hep;
dump_rx = hep->desc.bEndpointAddress
& USB_ENDPOINT_DIR_MASK;
dump_tx = !dump_rx;
"max %04x type %02x; "
"dev %d hub %d port %d"
"\n",
- bEnd,
+ epnum,
hw_ep->rx_double_buffered
? "2buf" : "1buf",
musb_readw(regs, MGC_O_HDRC_RXCSR),
musb_readb(regs, MGC_O_HDRC_RXTYPE),
/* FIXME: assumes multipoint */
musb_readb(musb->mregs,
- MGC_BUSCTL_OFFSET(bEnd,
+ MGC_BUSCTL_OFFSET(epnum,
MGC_O_HDRC_RXFUNCADDR)),
musb_readb(musb->mregs,
- MGC_BUSCTL_OFFSET(bEnd,
+ MGC_BUSCTL_OFFSET(epnum,
MGC_O_HDRC_RXHUBADDR)),
musb_readb(musb->mregs,
- MGC_BUSCTL_OFFSET(bEnd,
+ MGC_BUSCTL_OFFSET(epnum,
MGC_O_HDRC_RXHUBPORT))
);
if (code <= 0)
max -= code;
if (is_cppi_enabled()
- && bEnd
+ && epnum
&& hw_ep->rx_channel) {
- unsigned cppi = bEnd - 1;
+ unsigned cppi = epnum - 1;
unsigned off1 = cppi << 2;
void __iomem *base;
void __iomem *ram;
code = min(code, (int) max);
buf += code;
max -= code;
- } else if (musb->periodic[bEnd]) {
- code = dump_qh(musb->periodic[bEnd],
+ } else if (musb->periodic[epnum]) {
+ code = dump_qh(musb->periodic[epnum],
buf, max);
if (code <= 0)
break;
"max %04x type %02x; "
"dev %d hub %d port %d"
"\n",
- bEnd,
+ epnum,
hw_ep->tx_double_buffered
? "2buf" : "1buf",
musb_readw(regs, MGC_O_HDRC_TXCSR),
musb_readb(regs, MGC_O_HDRC_TXTYPE),
/* FIXME: assumes multipoint */
musb_readb(musb->mregs,
- MGC_BUSCTL_OFFSET(bEnd,
+ MGC_BUSCTL_OFFSET(epnum,
MGC_O_HDRC_TXFUNCADDR)),
musb_readb(musb->mregs,
- MGC_BUSCTL_OFFSET(bEnd,
+ MGC_BUSCTL_OFFSET(epnum,
MGC_O_HDRC_TXHUBADDR)),
musb_readb(musb->mregs,
- MGC_BUSCTL_OFFSET(bEnd,
+ MGC_BUSCTL_OFFSET(epnum,
MGC_O_HDRC_TXHUBPORT))
);
if (code <= 0)
max -= code;
if (is_cppi_enabled()
- && bEnd
+ && epnum
&& hw_ep->tx_channel) {
- unsigned cppi = bEnd - 1;
+ unsigned cppi = epnum - 1;
void __iomem *base;
void __iomem *ram;
code = min(code, (int) max);
buf += code;
max -= code;
- } else if (musb->periodic[bEnd]) {
- code = dump_qh(musb->periodic[bEnd],
+ } else if (musb->periodic[epnum]) {
+ code = dump_qh(musb->periodic[epnum],
buf, max);
if (code <= 0)
break;
if (is_peripheral_active(musb)) {
code = 0;
- if (hw_ep->ep_in.desc || !bEnd) {
+ if (hw_ep->ep_in.desc || !epnum) {
code = dump_ep(&hw_ep->ep_in, buf, max);
if (code <= 0)
break;
int code = 0;
unsigned long flags;
struct musb *musb = data;
- unsigned bEnd;
+ unsigned epnum;
count -= off;
count -= 1; /* for NUL at end */
/* generate the report for the end points */
// REVISIT ... not unless something's connected!
- for (bEnd = 0; count >= 0 && bEnd < musb->nr_endpoints;
- bEnd++) {
- code = dump_end_info(musb, bEnd, buffer, count);
+ for (epnum = 0; count >= 0 && epnum < musb->nr_endpoints;
+ epnum++) {
+ code = dump_end_info(musb, epnum, buffer, count);
if (code > 0) {
buffer += code;
count -= code;
/* TUSB mapping: "flat" plus ep0 special cases */
#if defined(CONFIG_USB_TUSB6010)
-#define MGC_SelectEnd(_mbase, _bEnd) \
- musb_writeb((_mbase), MGC_O_HDRC_INDEX, (_bEnd))
+#define MGC_SelectEnd(_mbase, _epnum) \
+ musb_writeb((_mbase), MGC_O_HDRC_INDEX, (_epnum))
#define MGC_END_OFFSET MGC_TUSB_OFFSET
/* "flat" mapping: each endpoint has its own i/o address */
#elif defined(MUSB_FLAT_REG)
-#define MGC_SelectEnd(_mbase, _bEnd) (((void)(_mbase)),((void)(_bEnd)))
+#define MGC_SelectEnd(_mbase, _epnum) (((void)(_mbase)),((void)(_epnum)))
#define MGC_END_OFFSET MGC_FLAT_OFFSET
/* "indexed" mapping: INDEX register controls register bank select */
#else
-#define MGC_SelectEnd(_mbase, _bEnd) \
- musb_writeb((_mbase), MGC_O_HDRC_INDEX, (_bEnd))
+#define MGC_SelectEnd(_mbase, _epnum) \
+ musb_writeb((_mbase), MGC_O_HDRC_INDEX, (_epnum))
#define MGC_END_OFFSET MGC_INDEXED_OFFSET
#endif
#define MGC_O_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
/* offsets to endpoint registers in indexed model (using INDEX register) */
-#define MGC_INDEXED_OFFSET(_bEnd, _bOffset) \
+#define MGC_INDEXED_OFFSET(_epnum, _bOffset) \
(0x10 + (_bOffset))
/* offsets to endpoint registers in flat models */
-#define MGC_FLAT_OFFSET(_bEnd, _bOffset) \
- (0x100 + (0x10*(_bEnd)) + (_bOffset))
+#define MGC_FLAT_OFFSET(_epnum, _bOffset) \
+ (0x100 + (0x10*(_epnum)) + (_bOffset))
#ifdef CONFIG_USB_TUSB6010
/* TUSB6010 EP0 configuration register is special */
-#define MGC_TUSB_OFFSET(_bEnd, _bOffset) \
+#define MGC_TUSB_OFFSET(_epnum, _bOffset) \
(0x10 + _bOffset)
#include "tusb6010.h" /* needed "only" for TUSB_EP0_CONF */
#endif
#define MGC_O_HDRC_RXHUBADDR 0x06
#define MGC_O_HDRC_RXHUBPORT 0x07
-#define MGC_BUSCTL_OFFSET(_bEnd, _bOffset) \
- (0x80 + (8*(_bEnd)) + (_bOffset))
+#define MGC_BUSCTL_OFFSET(_epnum, _bOffset) \
+ (0x80 + (8*(_epnum)) + (_bOffset))
/*
* MUSBHDRC Register bit masks
u32 len;
u16 wMaxPacketSize;
u8 bIndex;
- u8 bEnd;
+ u8 epnum;
u8 bTransmit;
};
pImplChannel = &(pController->aChannel[bBit]);
pImplChannel->pController = pController;
pImplChannel->bIndex = bBit;
- pImplChannel->bEnd = hw_ep->epnum;
+ pImplChannel->epnum = hw_ep->epnum;
pImplChannel->bTransmit = bTransmit;
pChannel = &(pImplChannel->Channel);
pChannel->pPrivateData = pImplChannel;
}
}
- wCsr |= (pImplChannel->bEnd << MGC_S_HSDMA_ENDPOINT)
+ wCsr |= (pImplChannel->epnum << MGC_S_HSDMA_ENDPOINT)
| (1 << MGC_S_HSDMA_ENABLE)
| (1 << MGC_S_HSDMA_IRQENABLE)
| (pImplChannel->bTransmit ? (1 << MGC_S_HSDMA_TRANSMIT) : 0);
(struct musb_dma_channel *) pChannel->pPrivateData;
DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
- pImplChannel->bEnd,
+ pImplChannel->epnum,
pImplChannel->bTransmit ? "Tx" : "Rx",
wPacketSize, dma_addr, dwLength, bMode);
if (pImplChannel->bTransmit) {
csr = musb_readw(mbase,
- MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_TXCSR));
+ MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_TXCSR));
csr &= ~(MGC_M_TXCSR_AUTOSET |
MGC_M_TXCSR_DMAENAB |
MGC_M_TXCSR_DMAMODE);
musb_writew(mbase,
- MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_TXCSR),
+ MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_TXCSR),
csr);
}
else {
csr = musb_readw(mbase,
- MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_RXCSR));
+ MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_RXCSR));
csr &= ~(MGC_M_RXCSR_AUTOCLEAR |
MGC_M_RXCSR_DMAENAB |
MGC_M_RXCSR_DMAMODE);
musb_writew(mbase,
- MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_RXCSR),
+ MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_RXCSR),
csr);
}
) {
/* Send out the packet */
MGC_SelectEnd(mbase,
- pImplChannel->bEnd);
+ pImplChannel->epnum);
musb_writew(mbase,
- MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_TXCSR),
+ MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_TXCSR),
MGC_M_TXCSR_TXPKTRDY);
} else
musb_dma_completion(
pController->pDmaPrivate,
- pImplChannel->bEnd,
+ pImplChannel->epnum,
pImplChannel->bTransmit);
}
}
if (bIntrUSB & MGC_M_INTR_SOF) {
void __iomem *mbase = musb->mregs;
struct musb_hw_ep *ep;
- u8 bEnd;
+ u8 epnum;
u16 wFrame;
DBG(6, "START_OF_FRAME\n");
/* start any periodic Tx transfers waiting for current frame */
wFrame = musb_readw(mbase, MGC_O_HDRC_FRAME);
ep = musb->endpoints;
- for (bEnd = 1; (bEnd < musb->nr_endpoints)
- && (musb->wEndMask >= (1 << bEnd));
- bEnd++, ep++) {
+ for (epnum = 1; (epnum < musb->nr_endpoints)
+ && (musb->wEndMask >= (1 << epnum));
+ epnum++, ep++) {
// FIXME handle framecounter wraps (12 bits)
// eliminate duplicated StartUrb logic
if (ep->dwWaitFrame >= wFrame) {
ep->dwWaitFrame = 0;
printk("SOF --> periodic TX%s on %d\n",
ep->tx_channel ? " DMA" : "",
- bEnd);
+ epnum);
if (!ep->tx_channel)
- musb_h_tx_start(musb, bEnd);
+ musb_h_tx_start(musb, epnum);
else
- cppi_hostdma_start(musb, bEnd);
+ cppi_hostdma_start(musb, epnum);
}
} /* end of for loop */
}
*/
static int __init ep_config_from_hw(struct musb *musb)
{
- u8 bEnd = 0, reg;
+ u8 epnum = 0, reg;
struct musb_hw_ep *hw_ep;
void *mbase = musb->mregs;
/* FIXME pick up ep0 maxpacket size */
- for (bEnd = 1; bEnd < MUSB_C_NUM_EPS; bEnd++) {
- MGC_SelectEnd(mbase, bEnd);
- hw_ep = musb->endpoints + bEnd;
+ for (epnum = 1; epnum < MUSB_C_NUM_EPS; epnum++) {
+ MGC_SelectEnd(mbase, epnum);
+ hw_ep = musb->endpoints + epnum;
/* read from core using indexed model */
reg = musb_readb(hw_ep->regs, 0x10 + MGC_O_HDRC_FIFOSIZE);
break;
}
musb->nr_endpoints++;
- musb->wEndMask |= (1 << bEnd);
+ musb->wEndMask |= (1 << epnum);
hw_ep->wMaxPacketSizeTx = 1 << (reg & 0x0f);
projects / linux-2.6-omap-h63xx.git / commitdiff