[ARM] 5417/1: Set the correct cacheid for ARMv6 CPUs with ARMv7 style MMU

The cacheid_init() function assumes that if cpu_architecture() returns
7, the caches are VIPT_NONALIASING. The cpu_architecture() function
returns the version of the supported MMU features (e.g. TEX remapping)
but it doesn't make any assumptions about the cache type. The patch adds
the checking of the Cache Type Register for the ARMv7 format.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 7049815d66d566e7d89c08fd3c25e33b8c48c995..68d6494c0389751d5584e94e833ae139ae53d76b 100644 (file)
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -233,12 +233,13 @@ static void __init cacheid_init(void)
        unsigned int cachetype = read_cpuid_cachetype();
        unsigned int arch = cpu_architecture();
 
-       if (arch >= CPU_ARCH_ARMv7) {
-               cacheid = CACHEID_VIPT_NONALIASING;
-               if ((cachetype & (3 << 14)) == 1 << 14)
-                       cacheid |= CACHEID_ASID_TAGGED;
-       } else if (arch >= CPU_ARCH_ARMv6) {
-               if (cachetype & (1 << 23))
+       if (arch >= CPU_ARCH_ARMv6) {
+               if ((cachetype & (7 << 29)) == 4 << 29) {
+                       /* ARMv7 register format */
+                       cacheid = CACHEID_VIPT_NONALIASING;
+                       if ((cachetype & (3 << 14)) == 1 << 14)
+                               cacheid |= CACHEID_ASID_TAGGED;
+               } else if (cachetype & (1 << 23))
                        cacheid = CACHEID_VIPT_ALIASING;
                else
                        cacheid = CACHEID_VIPT_NONALIASING;