cxgb3: prefetch buffer access in GRO mode

Elmininate a cache miss when accessing the CPL header within
the first aggregated buffer.

Signed-off-by: Divy Le Ray <divy@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/cxgb3/sge.c b/drivers/net/cxgb3/sge.c
index 90f6f82d3bf238472a9b062822ddb8e6f760a817..a482429846eb40e78141f54bff7168e2ddf91a4f 100644 (file)
--- a/drivers/net/cxgb3/sge.c
+++ b/drivers/net/cxgb3/sge.c
@@ -2029,6 +2029,8 @@ static void lro_add_page(struct adapter *adap, struct sge_qset *qs,
        pci_unmap_single(adap->pdev, pci_unmap_addr(sd, dma_addr),
                         fl->buf_size, PCI_DMA_FROMDEVICE);
 
+       prefetch(&qs->lro_frag_tbl);
+
        rx_frag += nr_frags;
        rx_frag->page = sd->pg_chunk.page;
        rx_frag->page_offset = sd->pg_chunk.offset + offset;
@@ -2997,6 +2999,7 @@ int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
                     V_NEWTIMER(q->rspq.holdoff_tmr));
 
        mod_timer(&q->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
+
        return 0;
 
 err_unlock: