]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
powerpc: Add documentation for CPM GPIO banks
authorJochen Friedrich <jochen@scram.de>
Sat, 5 Jul 2008 11:29:28 +0000 (13:29 +0200)
committerKumar Gala <galak@kernel.crashing.org>
Wed, 16 Jul 2008 22:57:40 +0000 (17:57 -0500)
Signed-off-by: Jochen Friedrich <jochen@scram.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt [new file with mode: 0644]

diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt
new file mode 100644 (file)
index 0000000..1815dfe
--- /dev/null
@@ -0,0 +1,38 @@
+Every GPIO controller node must have #gpio-cells property defined,
+this information will be used to translate gpio-specifiers.
+
+On CPM1 devices, all ports are using slightly different register layouts.
+Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.
+
+On CPM2 devices, all ports are 32bit ports and use a common register layout.
+
+Required properties:
+- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
+  "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
+  "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
+- #gpio-cells : Should be two. The first cell is the pin number and the
+  second cell is used to specify optional paramters (currently unused).
+- gpio-controller : Marks the port as GPIO controller.
+
+Example of three SOC GPIO banks defined as gpio-controller nodes:
+
+       CPM1_PIO_A: gpio-controller@950 {
+               #gpio-cells = <2>;
+               compatible = "fsl,cpm1-pario-bank-a";
+               reg = <0x950 0x10>;
+               gpio-controller;
+       };
+
+       CPM1_PIO_B: gpio-controller@ab8 {
+               #gpio-cells = <2>;
+               compatible = "fsl,cpm1-pario-bank-b";
+               reg = <0xab8 0x10>;
+               gpio-controller;
+       };
+
+       CPM1_PIO_E: gpio-controller@ac8 {
+               #gpio-cells = <2>;
+               compatible = "fsl,cpm1-pario-bank-e";
+               reg = <0xac8 0x18>;
+               gpio-controller;
+       };