/* 2420 Sysboot setup (2430 is different) */
static u32 get_sysboot_value(void)
{
- return (omap_readl(OMAP24XX_CONTROL_STATUS) & 0xFFF);
+ return (omap_readl(OMAP2_CONTROL_STATUS) & 0xFFF);
}
/* FIXME: This function should be moved to some other file, gpmc.c? */
* Module Input Clock selection
*/
if (cpu_is_omap24xx()) {
- u32 v = omap_readl(OMAP24XX_CONTROL_DEVCONF);
+ u32 v = omap_readl(OMAP2_CONTROL_DEVCONF);
v |= (1 << 24);
- omap_writel(v, OMAP24XX_CONTROL_DEVCONF);
+ omap_writel(v, OMAP2_CONTROL_DEVCONF);
}
}
mmc1_conf = *mmc;
#define OMAP24XX_IVA_INTC_BASE 0x40000000
#define IRQ_SIR_IRQ 0x0040
-#define OMAP24XX_CONTROL_DEVCONF (L4_24XX_BASE + 0x274)
-#define OMAP24XX_CONTROL_STATUS (L4_24XX_BASE + 0x2f8)
-
#define OMAP2420_CTRL_BASE L4_24XX_BASE
#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
#endif
+/* Control module */
+#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CTRL_BASE + 0x274)
+#define OMAP2_CONTROL_DEVCONF1 (OMAP2_CTRL_BASE + 0x2e8)
+#define OMAP2_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0
+
+#define OMAP2_CONTROL_STATUS (OMAP2_CTRL_BASE + 0x2f8)
+
#endif /* __ASM_ARCH_OMAP24XX_H */