.set_rate = &omap2_clksel_set_rate
};
+/*
+ * Presumably this is the same as SSI_ICLK.
+ * TRM contradicts itself on what clockdomain SSI_ICLK is in
+ */
+static struct clk ssi_l4_ick = {
+ .name = "ssi_l4_ick",
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP24XX_EN_SSI_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
/*
* GFX clock domain
&usb_l4_ick,
/* L4 domain clocks */
&l4_ck, /* used as both core_l4 and wu_l4 */
+ &ssi_l4_ick,
/* virtual meta-group clock */
&virt_prcm_set,
/* general l4 interface ck, multi-parent functional clk */