[ARM] 4604/2: AT91: Master clock divistor on SAM9

The calculation for the Master clock divisor (MDIV) is different on the
SAM9 processors than on the AT91RM9200.

Orignal patch from Sascha Erlacher.

Also use the defined AT91_PMC_PRES instead of hard-coded bitmasks.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 848efb2a4ebfbc14cc7bf9426dadc04ca5c194e1..57c3b647ce834f06a790f04f48d18b11e7fd5d65 100644 (file)
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -351,7 +351,7 @@ static void init_programmable_clock(struct clk *clk)
        pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
        parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
        clk->parent = parent;
-       clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
+       clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
 }
 
 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
@@ -587,8 +587,11 @@ int __init at91_clock_init(unsigned long main_clock)
        mckr = at91_sys_read(AT91_PMC_MCKR);
        mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
        freq = mck.parent->rate_hz;
-       freq /= (1 << ((mckr >> 2) & 3));               /* prescale */
-       mck.rate_hz = freq / (1 + ((mckr >> 8) & 3));   /* mdiv */
+       freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
+       if (cpu_is_at91rm9200())
+               mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
+       else
+               mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
 
        /* Register the PMC's standard clocks */
        for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)