static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
{
unsigned int nob = data->blocks;
- unsigned int blksz = 1 << data->blksz_bits;
+ unsigned int blksz = data->blksz;
unsigned int datasz = nob * blksz;
int i;
int sync_dev = 0;
data_addr = io_v2p((u32) host->base) + OMAP_MMC_REG_DATA;
- frame = 1 << data->blksz_bits;
+ frame = data->blksz;
count = sg_dma_len(sg);
- if ((data->blocks == 1) && (count > (1 << data->blksz_bits)))
+ if ((data->blocks == 1) && (count > data->blksz))
count = frame;
host->dma_len = count;
}
- block_size = 1 << data->blksz_bits;
+ block_size = data->blksz;
OMAP_MMC_WRITE(host->base, NBLK, data->blocks - 1);
OMAP_MMC_WRITE(host->base, BLEN, block_size - 1);
}
DBG("blksz %04x blks %04x flags %08x\n",
- 1 << data->blksz_bits, data->blocks, data->flags);
+ data->blksz, data->blocks, data->flags);
DBG("tsac %d ms nsac %d clk\n",
data->timeout_ns / 1000000, data->timeout_clks);
writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
- writew(1 << data->blksz_bits, host->ioaddr + SDHCI_BLOCK_SIZE);
+ writew(data->blksz, host->ioaddr + SDHCI_BLOCK_SIZE);
writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
if (host->flags & SDHCI_USE_DMA) {
writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
} else {
- host->size = (1 << data->blksz_bits) * data->blocks;
+ host->size = data->blksz * data->blocks;
host->cur_sg = data->sg;
host->num_sg = data->sg_len;
blocks = 0;
else
blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
- data->bytes_xfered = (1 << data->blksz_bits) * (data->blocks - blocks);
+ data->bytes_xfered = data->blksz * (data->blocks - blocks);
if ((data->error == MMC_ERR_NONE) && blocks) {
printk(KERN_ERR "%s: Controller signalled completion even "