[PATCH] ppc64: Fix runlatch code to work on pseries machines

Not all ppc64 CPUs have the CTRL SPR, so we need a cputable feature for it.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

diff --git a/arch/ppc64/kernel/cputable.c b/arch/ppc64/kernel/cputable.c
index c301366176ef142456db8985d3668dbccc2de529..8d4c46f6f0b62ef8bb9f1d5e085f7f74f9e5cf99 100644 (file)
--- a/arch/ppc64/kernel/cputable.c
+++ b/arch/ppc64/kernel/cputable.c
@@ -81,7 +81,7 @@ struct cpu_spec       cpu_specs[] = {
                .cpu_name               = "RS64-II (northstar)",
                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
-                       CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+                       CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
                .cpu_user_features      = COMMON_USER_PPC64,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
@@ -94,7 +94,7 @@ struct cpu_spec       cpu_specs[] = {
                .cpu_name               = "RS64-III (pulsar)",
                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
-                       CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+                       CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
                .cpu_user_features      = COMMON_USER_PPC64,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
@@ -107,7 +107,7 @@ struct cpu_spec     cpu_specs[] = {
                .cpu_name               = "RS64-III (icestar)",
                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
-                       CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+                       CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
                .cpu_user_features      = COMMON_USER_PPC64,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
@@ -120,7 +120,7 @@ struct cpu_spec     cpu_specs[] = {
                .cpu_name               = "RS64-IV (sstar)",
                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
-                       CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+                       CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
                .cpu_user_features      = COMMON_USER_PPC64,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,

diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h
index cbbfbec78b6bde7ec6eb9d6a05dcb56bd3d3b030..d67fa9e2607908477b8517df6a5ffe8bb9934337 100644 (file)
--- a/include/asm-ppc64/cputable.h
+++ b/include/asm-ppc64/cputable.h
@@ -138,6 +138,7 @@ extern firmware_feature_t firmware_features_table[];
 #define CPU_FTR_COHERENT_ICACHE        ASM_CONST(0x0000020000000000)
 #define CPU_FTR_LOCKLESS_TLBIE         ASM_CONST(0x0000040000000000)
 #define CPU_FTR_MMCRA_SIHV             ASM_CONST(0x0000080000000000)
+#define CPU_FTR_CTRL                   ASM_CONST(0x0000100000000000)
 
 /* Platform firmware features */
 #define FW_FTR_                                ASM_CONST(0x0000000000000001)
@@ -148,7 +149,7 @@ extern firmware_feature_t firmware_features_table[];
 
 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
                                  CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
-                                 CPU_FTR_NODSISRALIGN)
+                                 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
 
 /* iSeries doesn't support large pages */
 #ifdef CONFIG_PPC_ISERIES

diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h
index af28aa55d8c1fe1cec34a17760af92a02c77ab3e..06aa07c2c71d1ed63f2e62899ac2c177aab61354 100644 (file)
--- a/include/asm-ppc64/processor.h
+++ b/include/asm-ppc64/processor.h
@@ -20,6 +20,7 @@
 #include <asm/ptrace.h>
 #include <asm/types.h>
 #include <asm/systemcfg.h>
+#include <asm/cputable.h>
 
 /* Machine State Register (MSR) Fields */
 #define MSR_SF_LG      63              /* Enable 64 bit mode */
@@ -501,18 +502,22 @@ static inline void ppc64_runlatch_on(void)
 {
        unsigned long ctrl;
 
-       ctrl = mfspr(SPRN_CTRLF);
-       ctrl |= CTRL_RUNLATCH;
-       mtspr(SPRN_CTRLT, ctrl);
+       if (cpu_has_feature(CPU_FTR_CTRL)) {
+               ctrl = mfspr(SPRN_CTRLF);
+               ctrl |= CTRL_RUNLATCH;
+               mtspr(SPRN_CTRLT, ctrl);
+       }
 }
 
 static inline void ppc64_runlatch_off(void)
 {
        unsigned long ctrl;
 
-       ctrl = mfspr(SPRN_CTRLF);
-       ctrl &= ~CTRL_RUNLATCH;
-       mtspr(SPRN_CTRLT, ctrl);
+       if (cpu_has_feature(CPU_FTR_CTRL)) {
+               ctrl = mfspr(SPRN_CTRLF);
+               ctrl &= ~CTRL_RUNLATCH;
+               mtspr(SPRN_CTRLT, ctrl);
+       }
 }
 
 #endif /* __KERNEL__ */