}
void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
- int frame_count, int sync_mode)
+ int frame_count, int sync_mode,
+ int dma_trigger, int src_or_dst_synch)
{
u16 w;
omap_writew(w, OMAP_DMA_LCH_CTRL(lch));
}
-
void omap_set_dma_src_params(int lch, int src_port, int src_amode,
- unsigned long src_start)
+ unsigned long src_start,
+ int src_ei, int src_fi)
{
u16 w;
}
void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
- unsigned long dest_start)
+ unsigned long dest_start,
+ int dst_ei, int dst_fi)
{
u16 w;
omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
OMAP_DMA_DATA_TYPE_S16,
length >> 1, 1,
- OMAP_DMA_SYNC_ELEMENT);
+ OMAP_DMA_SYNC_ELEMENT,
+ 0, 0);
omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
OMAP_DMA_PORT_TIPB,
OMAP_DMA_AMODE_CONSTANT,
- mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1);
+ mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
+ 0, 0);
omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
OMAP_DMA_PORT_EMIFF,
OMAP_DMA_AMODE_POST_INC,
- buffer);
+ buffer,
+ 0, 0);
omap_start_dma(mcbsp[id].dma_tx_lch);
wait_for_completion(&(mcbsp[id].tx_dma_completion));
omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
OMAP_DMA_DATA_TYPE_S16,
length >> 1, 1,
- OMAP_DMA_SYNC_ELEMENT);
+ OMAP_DMA_SYNC_ELEMENT,
+ 0, 0);
omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
OMAP_DMA_PORT_TIPB,
OMAP_DMA_AMODE_CONSTANT,
- mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1);
+ mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
+ 0, 0);
omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
OMAP_DMA_PORT_EMIFF,
OMAP_DMA_AMODE_POST_INC,
- buffer);
+ buffer,
+ 0, 0);
omap_start_dma(mcbsp[id].dma_rx_lch);
wait_for_completion(&(mcbsp[id].rx_dma_completion));
if (machine_is_omap_h3())
omap_set_dma_src_params(dmach, OMAP_DMA_PORT_OCP_T1,
- OMAP_DMA_AMODE_CONSTANT, CAM_CAMDATA_REG);
+ OMAP_DMA_AMODE_CONSTANT, CAM_CAMDATA_REG,
+ 0, 0);
else
omap_set_dma_src_params(dmach, OMAP_DMA_PORT_TIPB,
- OMAP_DMA_AMODE_CONSTANT, CAM_CAMDATA_REG);
+ OMAP_DMA_AMODE_CONSTANT, CAM_CAMDATA_REG,
+ 0, 0);
omap_set_dma_dest_params(dmach, OMAP_DMA_PORT_EMIFF,
- OMAP_DMA_AMODE_POST_INC, sg_dma_address(sglist));
+ OMAP_DMA_AMODE_POST_INC, sg_dma_address(sglist),
+ 0, 0);
omap_set_dma_transfer_params(dmach, OMAP_DMA_DATA_TYPE_S32,
FIFO_TRIGGER_LVL,
sg_dma_len(sglist)/(4 * FIFO_TRIGGER_LVL),
- OMAP_DMA_SYNC_FRAME);
+ OMAP_DMA_SYNC_FRAME,
+ 0, 0);
omap_writew(omap_readw(OMAP_DMA_CLNK_CTRL(dmach)) & ~(1<<15),
buf = 0x800f | ((frame - 1) << 8);
omap_set_dma_src_params(dma_ch, OMAP_DMA_PORT_TIPB,
OMAP_DMA_AMODE_CONSTANT,
- data_addr);
+ data_addr,
+ 0, 0);
omap_set_dma_dest_params(dma_ch, OMAP_DMA_PORT_EMIFF,
OMAP_DMA_AMODE_POST_INC,
- sg_dma_address(sg));
+ sg_dma_address(sg),
+ 0, 0);
omap_set_dma_dest_data_pack(dma_ch, 1);
omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
} else {
buf = 0x0f80 | ((frame - 1) << 0);
omap_set_dma_dest_params(dma_ch, OMAP_DMA_PORT_TIPB,
OMAP_DMA_AMODE_CONSTANT,
- data_addr);
+ data_addr,
+ 0, 0);
omap_set_dma_src_params(dma_ch, OMAP_DMA_PORT_EMIFF,
OMAP_DMA_AMODE_POST_INC,
- sg_dma_address(sg));
+ sg_dma_address(sg),
+ 0, 0);
omap_set_dma_src_data_pack(dma_ch, 1);
omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
}
OMAP_MMC_WRITE(host->base, BUF, buf);
omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
- frame, count, OMAP_DMA_SYNC_FRAME);
+ frame, count, OMAP_DMA_SYNC_FRAME,
+ 0, 0);
}
/* a scatterlist segment completed */
fifo_reg = NAND_BASE + NND_FIFO;
if (is_write) {
omap_set_dma_dest_params(dma_ch, OMAP_DMA_PORT_TIPB,
- OMAP_DMA_AMODE_CONSTANT, fifo_reg);
+ OMAP_DMA_AMODE_CONSTANT, fifo_reg,
+ 0, 0);
omap_set_dma_src_params(dma_ch, OMAP_DMA_PORT_EMIFF,
OMAP_DMA_AMODE_POST_INC,
- virt_to_phys(addr));
+ virt_to_phys(addr),
+ 0, 0);
// omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
/* Set POSTWRITE bit */
nand_write_reg(NND_CTRL, nand_read_reg(NND_CTRL) | (1 << 16));
} else {
omap_set_dma_src_params(dma_ch, OMAP_DMA_PORT_TIPB,
- OMAP_DMA_AMODE_CONSTANT, fifo_reg);
+ OMAP_DMA_AMODE_CONSTANT, fifo_reg,
+ 0, 0);
omap_set_dma_dest_params(dma_ch, OMAP_DMA_PORT_EMIFF,
OMAP_DMA_AMODE_POST_INC,
- virt_to_phys(addr));
+ virt_to_phys(addr),
+ 0, 0);
// omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_8);
/* Set PREFETCH bit */
nand_write_reg(NND_CTRL, nand_read_reg(NND_CTRL) | (1 << 17));
}
omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, block_size / 4,
- block_count, OMAP_DMA_SYNC_FRAME);
+ block_count, OMAP_DMA_SYNC_FRAME,
+ 0, 0);
init_completion(&comp);
len = u32_count << 2;
static void omap1610_irda_start_rx_dma(struct omap1610_irda *si)
{
/* Configure DMA */
- omap_set_dma_src_params(si->rx_dma_channel, 0x3, 0x0, (unsigned long)UART3_RHR);
+ omap_set_dma_src_params(si->rx_dma_channel, 0x3, 0x0, (unsigned long)UART3_RHR,
+ 0, 0);
omap_enable_dma_irq(si->rx_dma_channel, 0x01);
omap_set_dma_dest_params(si->rx_dma_channel, 0x0, 0x1,
- si->rx_buf_dma_phys);
+ si->rx_buf_dma_phys,
+ 0, 0);
- omap_set_dma_transfer_params(si->rx_dma_channel, 0x0, 4096, 0x1, 0x0);
+ omap_set_dma_transfer_params(si->rx_dma_channel, 0x0, 4096, 0x1, 0x0, 0, 0);
omap_start_dma(si->rx_dma_channel);
}
__ECHO_IN;
/* Configure DMA */
- omap_set_dma_dest_params(si->tx_dma_channel, 0x03, 0x0, (unsigned long)UART3_THR);
-
+ omap_set_dma_dest_params(si->tx_dma_channel, 0x03, 0x0, (unsigned long)UART3_THR,
+ 0, 0);
omap_enable_dma_irq(si->tx_dma_channel, 0x01);
omap_set_dma_src_params(si->tx_dma_channel, 0x0, 0x1,
- si->tx_buf_dma_phys);
+ si->tx_buf_dma_phys,
+ 0, 0);
- omap_set_dma_transfer_params(si->tx_dma_channel, 0x0, size, 0x1, 0x0);
+ omap_set_dma_transfer_params(si->tx_dma_channel, 0x0, size, 0x1, 0x0, 0, 0);
HDBG1(1);
|| (cpu_is_omap15xx() && length < ep->maxpacket)) {
txdma_ctrl = UDC_TXN_EOT | length;
omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
- length, 1, sync_mode);
+ length, 1, sync_mode, 0, 0);
} else {
length = min(length / ep->maxpacket,
(unsigned) UDC_TXN_TSC + 1);
txdma_ctrl = length;
omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
- ep->ep.maxpacket >> 1, length, sync_mode);
+ ep->ep.maxpacket >> 1, length, sync_mode,
+ 0, 0);
length *= ep->maxpacket;
}
omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
- OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual);
+ OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
+ 0, 0);
omap_start_dma(ep->lch);
ep->dma_counter = dma_csac(ep->lch);
req->dma_bytes = packets * ep->ep.maxpacket;
omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
ep->ep.maxpacket >> 1, packets,
- OMAP_DMA_SYNC_ELEMENT);
+ OMAP_DMA_SYNC_ELEMENT,
+ 0, 0);
omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
- OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual);
+ OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
+ 0, 0);
ep->dma_counter = DMA_DEST_LAST(ep->lch);
UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
omap_set_dma_dest_params(ep->lch,
OMAP_DMA_PORT_TIPB,
OMAP_DMA_AMODE_CONSTANT,
- (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG));
+ (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
+ 0, 0);
}
} else {
status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
omap_set_dma_src_params(ep->lch,
OMAP_DMA_PORT_TIPB,
OMAP_DMA_AMODE_CONSTANT,
- (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG));
+ (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
+ 0, 0);
/* EMIFF */
omap_set_dma_dest_burst_mode(ep->lch,
OMAP_DMA_DATA_BURST_4);
extern void omap_stop_dma(int lch);
extern void omap_set_dma_transfer_params(int lch, int data_type,
int elem_count, int frame_count,
- int sync_mode);
+ int sync_mode,
+ int dma_trigger, int src_or_dst_synch);
extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
u32 color);
extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
- unsigned long src_start);
+ unsigned long src_start,
+ int src_ei, int src_fi);
extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
extern void omap_set_dma_src_data_pack(int lch, int enable);
extern void omap_set_dma_src_burst_mode(int lch,
enum omap_dma_burst_mode burst_mode);
extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
- unsigned long dest_start);
+ unsigned long dest_start,
+ int dst_ei, int dst_fi);
extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
extern void omap_set_dma_dest_data_pack(int lch, int enable);
extern void omap_set_dma_dest_burst_mode(int lch,
int cfn = dma_size / (2 * cen);
FN_IN;
omap_set_dma_dest_params(channel, 0x05, 0x00,
- (OMAP1610_MCBSP1_BASE + 0x806));
- omap_set_dma_src_params(channel, 0x00, 0x01, dma_ptr);
- omap_set_dma_transfer_params(channel, dt, cen, cfn, 0x00);
+ (OMAP1610_MCBSP1_BASE + 0x806),
+ 0, 0);
+ omap_set_dma_src_params(channel, 0x00, 0x01, dma_ptr,
+ 0, 0);
+ omap_set_dma_transfer_params(channel, dt, cen, cfn, 0x00, 0, 0);
FN_OUT(0);
return 0;
}
int cfn = dma_size / (2 * cen);
FN_IN;
omap_set_dma_src_params(channel, 0x05, 0x00,
- (OMAP1610_MCBSP1_BASE + 0x802));
- omap_set_dma_dest_params(channel, 0x00, 0x01, dma_ptr);
- omap_set_dma_transfer_params(channel, dt, cen, cfn, 0x00);
+ (OMAP1610_MCBSP1_BASE + 0x802),
+ 0, 0);
+ omap_set_dma_dest_params(channel, 0x00, 0x01, dma_ptr, 0, 0);
+ omap_set_dma_transfer_params(channel, dt, cen, cfn, 0x00, 0, 0);
FN_OUT(0);
return 0;
}
int cfn = dma_size / (2 * cen);
FN_IN;
omap_set_dma_dest_params(channel, 0x05, 0x00,
- (OMAP1610_MCBSP1_BASE + 0x806));
- omap_set_dma_src_params(channel, 0x00, 0x01, dma_ptr);
- omap_set_dma_transfer_params(channel, dt, cen, cfn, 0x00);
+ (OMAP1610_MCBSP1_BASE + 0x806),
+ 0, 0);
+ omap_set_dma_src_params(channel, 0x00, 0x01, dma_ptr, 0, 0);
+ omap_set_dma_transfer_params(channel, dt, cen, cfn, 0x00, 0, 0);
FN_OUT(0);
return 0;
}
int cfn = dma_size / (2 * cen);
FN_IN;
omap_set_dma_src_params(channel, 0x05, 0x00,
- (OMAP1610_MCBSP1_BASE + 0x802));
- omap_set_dma_dest_params(channel, 0x00, 0x01, dma_ptr);
- omap_set_dma_transfer_params(channel, dt, cen, cfn, 0x00);
+ (OMAP1610_MCBSP1_BASE + 0x802),
+ 0, 0);
+ omap_set_dma_dest_params(channel, 0x00, 0x01, dma_ptr, 0, 0);
+ omap_set_dma_transfer_params(channel, dt, cen, cfn, 0x00, 0, 0);
FN_OUT(0);
return 0;
}