]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
3430 clock: revise SmartReflex clocks
authorPaul Walmsley <paul@pwsan.com>
Mon, 12 Nov 2007 10:57:27 +0000 (03:57 -0700)
committerTony Lindgren <tony@atomide.com>
Thu, 15 Nov 2007 22:11:15 +0000 (14:11 -0800)
The two SmartReflex voltage controllers on OMAP3430 have one
functional clock each.  These clocks appear to be independent of each
other.  Encode them appropriately, replacing the previous 'sr_alwon_fck'
clock.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/mach-omap2/clock34xx.h

index 8fd46d4fb7f0f806686f65957eacacb6d078901f..d6dea3978a1540658ef1581f51d15a187aa85aee 100644 (file)
@@ -2012,11 +2012,23 @@ static struct clk mcbsp4_fck = {
 
 /* SR clocks */
 
-/* REVISIT: dependent on en_sr1 && en_sr2 - use custom enable/disable? */
-static struct clk sr_alwon_fck = {
-       .name           = "sr_alwon_fck",
+/* SmartReflex fclk (VDD1) */
+static struct clk sr1_fck = {
+       .name           = "sr1_fck",
        .parent         = &sys_ck,
-       .flags          = CLOCK_IN_OMAP343X,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_bit     = OMAP3430_EN_SR1_SHIFT,
+       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+       .recalc         = &followparent_recalc,
+};
+
+/* SmartReflex fclk (VDD2) */
+static struct clk sr2_fck = {
+       .name           = "sr2_fck",
+       .parent         = &sys_ck,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_bit     = OMAP3430_EN_SR2_SHIFT,
+       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
        .recalc         = &followparent_recalc,
 };
 
@@ -2213,7 +2225,8 @@ static struct clk *onchip_34xx_clks[] __initdata = {
        &mcbsp2_fck,
        &mcbsp3_fck,
        &mcbsp4_fck,
-       &sr_alwon_fck,
+       &sr1_fck,
+       &sr2_fck,
        &sr_l4_ick,
        &secure_32k_fck,
        &gpt12_fck,