switch (ctrlrequest->bRequest) {
case USB_REQ_SET_ADDRESS:
/* change it after the status stage */
- musb->bSetAddress = TRUE;
+ musb->set_address = TRUE;
musb->address = (u8) (ctrlrequest->wValue & 0x7f);
handled = 1;
break;
* the TX FIFO right away, and give the controller a moment
* to switch modes...
*/
- musb->bSetAddress = FALSE;
+ musb->set_address = FALSE;
musb->ackpend = MGC_M_CSR0_P_SVDRXPKTRDY;
if (req->wLength == 0) {
if (req->bRequestType & USB_DIR_IN)
* we get 10 msec to receive this irq... until this
* is done we won't see the next packet.
*/
- if (musb->bSetAddress) {
- musb->bSetAddress = FALSE;
+ if (musb->set_address) {
+ musb->set_address = FALSE;
musb_writeb(mbase, MGC_O_HDRC_FADDR, musb->address);
}
unsigned is_self_powered:1;
unsigned is_bus_powered:1;
- unsigned bSetAddress:1;
+ unsigned set_address:1;
unsigned test_mode:1;
unsigned softconnect:1;