x86: unmask CPUID levels on Intel CPUs, fix

Impact: fix boot hang on pre-model-15 Intel CPUs

rdmsrl_safe() does not work in very early bootup code yet, because we
dont have the pagefault handler installed yet so exception section
does not get parsed. rdmsr_safe() will just crash and hang the bootup.

So limit the MSR_IA32_MISC_ENABLE MSR read to those CPU types that
support it.

Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 43c1dcf0bec7a6ead00d7e62fd4e3fce50b6f1b7..549f2ada55f584bd045e13fb1e0c65a029f317e1 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -29,14 +29,17 @@
 
 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 {
-       u64 misc_enable;
-
-       /* Unmask CPUID levels if masked */
-       if (!rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_enable) &&
-           (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)) {
-               misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
-               wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
-               c->cpuid_level = cpuid_eax(0);
+       /* Unmask CPUID levels if masked: */
+       if (c->x86 == 6 && c->x86_model >= 15) {
+               u64 misc_enable;
+
+               rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+
+               if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
+                       misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
+                       wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+                       c->cpuid_level = cpuid_eax(0);
+               }
        }
 
        if ((c->x86 == 0xf && c->x86_model >= 0x03) ||