/* set pin as input */
x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
- x &= ~IOPM_(pin);
+ x &= ~IOPM(pin);
__raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM);
local_irq_restore(flags);
/* set pin as input */
x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
- x &= ~IOPM_(pin);
+ x &= ~IOPM(pin);
__raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM);
local_irq_restore(flags);
/* set line state */
x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
if (state)
- x |= (1 << pin);
+ x |= IOPD(pin);
else
- x &= ~(1 << pin);
+ x &= ~IOPD(pin);
__raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD);
/* set pin as output */
x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
- x |= IOPM_(pin);
+ x |= IOPM(pin);
__raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM);
local_irq_restore(flags);
/* set output line state */
x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
if (state)
- x |= (1 << pin);
+ x |= IOPD(pin);
else
- x &= ~(1 << pin);
+ x &= ~IOPD(pin);
__raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD);
local_irq_restore(flags);
return -EINVAL;
x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
- return (x & (1 << pin)) != 0;
+ return (x & IOPD(pin)) != 0;
}
EXPORT_SYMBOL(gpio_get_value);
for (i = KS8695_GPIO_0; i <= KS8695_GPIO_15 ; i++) {
seq_printf(s, "%i:\t", i);
- seq_printf(s, "%s\t", (mode & IOPM_(i)) ? "Output" : "Input");
+ seq_printf(s, "%s\t", (mode & IOPM(i)) ? "Output" : "Input");
if (i <= KS8695_GPIO_3) {
if (ctrl & enable[i]) {
seq_printf(s, "\t");
- seq_printf(s, "%i\n", (data & IOPD_(i)) ? 1 : 0);
+ seq_printf(s, "%i\n", (data & IOPD(i)) ? 1 : 0);
}
return 0;
}
/* Port Mode Register */
-#define IOPM_(x) (1 << (x)) /* Mode for GPIO Pin x */
+#define IOPM(x) (1 << (x)) /* Mode for GPIO Pin x */
/* Port Control Register */
#define IOPC_IOTIM1EN (1 << 17) /* GPIO Pin for Timer1 Enable */
#define IOPC_TM_EDGE (6) /* Both Edge Detection */
/* Port Data Register */
-#define IOPD_(x) (1 << (x)) /* Signal Level of GPIO Pin x */
+#define IOPD(x) (1 << (x)) /* Signal Level of GPIO Pin x */
#endif
#define KS8695_LRDLB (0x14) /* Receive Descriptor List Base Address */
#define KS8695_LMAL (0x18) /* MAC Station Address Low */
#define KS8695_LMAH (0x1c) /* MAC Station Address High */
-#define KS8695_LMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */
-#define KS8695_LMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */
+#define KS8695_LMAAL(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */
+#define KS8695_LMAAH(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */
/* DMA Transmit Control Register */
#define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */
#define KS8695_WMAL (0x18) /* MAC Station Address Low */
#define KS8695_WMAH (0x1c) /* MAC Station Address High */
-#define KS8695_WMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */
-#define KS8695_WMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */
+#define KS8695_WMAAL(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */
+#define KS8695_WMAAH(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */
/* DMA Transmit Control Register */