[ARM] S3C64XX: Add external interrupt group definitions

Add definitions for the external interrupt groups which accompany
the original IRQ_EINT from the s3c24xx series.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>

diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h
index 5ab41ad143b7a502b51affe5601acd7dd0edc732..bc25689c3f8376aef0e80c0a49cf3faeae97956a 100644 (file)
--- a/arch/arm/plat-s3c64xx/include/plat/irqs.h
+++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h
@@ -153,10 +153,44 @@
 #define S3C_EINT(x)            ((x) + S3C_IRQ_EINT_BASE)
 #define IRQ_EINT(x)            S3C_EINT(x)
 
-/* Define NR_IRQs here, machine specific can always re-define.
- * Currently the IRQ_EINT27 is the last one we can have. */
+/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
+ * that they are sourced from the GPIO pins but with a different scheme for
+ * priority and source indication.
+ *
+ * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
+ * interrupts, but for historical reasons they are kept apart from these
+ * next interrupts.
+ *
+ * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
+ * machine specific support files.
+ */
 
-#define NR_IRQS        (S3C_EINT(27) + 1)
+#define IRQ_EINT_GROUP1_NR     (15)
+#define IRQ_EINT_GROUP2_NR     (8)
+#define IRQ_EINT_GROUP3_NR     (5)
+#define IRQ_EINT_GROUP4_NR     (14)
+#define IRQ_EINT_GROUP5_NR     (7)
+#define IRQ_EINT_GROUP6_NR     (10)
+#define IRQ_EINT_GROUP7_NR     (16)
+#define IRQ_EINT_GROUP8_NR     (15)
+#define IRQ_EINT_GROUP9_NR     (9)
+
+#define IRQ_EINT_GROUP_BASE    S3C_EINT(28)
+#define IRQ_EINT_GROUP1_BASE   (IRQ_EINT_GROUP_BASE + 0x00)
+#define IRQ_EINT_GROUP2_BASE   (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
+#define IRQ_EINT_GROUP3_BASE   (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
+#define IRQ_EINT_GROUP4_BASE   (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
+#define IRQ_EINT_GROUP5_BASE   (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
+#define IRQ_EINT_GROUP6_BASE   (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
+#define IRQ_EINT_GROUP7_BASE   (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
+#define IRQ_EINT_GROUP8_BASE   (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
+#define IRQ_EINT_GROUP9_BASE   (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
+
+#define IRQ_EINT_GROUP(group, no)      (IRQ_EINT_GROUP##group##__BASE + (x))
+
+/* Set the default NR_IRQS */
+
+#define NR_IRQS        (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
 
 #endif /* __ASM_PLAT_S3C64XX_IRQS_H */