/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
#define MUSB_CSR0_P_WZC_BITS \
- ( MUSB_CSR0_P_SENTSTALL )
+ (MUSB_CSR0_P_SENTSTALL)
#define MUSB_CSR0_H_WZC_BITS \
- ( MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
- | MUSB_CSR0_RXPKTRDY )
+ (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
+ | MUSB_CSR0_RXPKTRDY)
/* TxType/RxType */
#define MUSB_TYPE_SPEED 0xc0
/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
#define MUSB_TXCSR_P_WZC_BITS \
- ( MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
- | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY )
+ (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
+ | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
#define MUSB_TXCSR_H_WZC_BITS \
- ( MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
- | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY )
+ (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
+ | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
/* RXCSR in Peripheral and Host mode */
#define MUSB_RXCSR_AUTOCLEAR 0x8000
/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
#define MUSB_RXCSR_P_WZC_BITS \
- ( MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
- | MUSB_RXCSR_RXPKTRDY )
+ (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
+ | MUSB_RXCSR_RXPKTRDY)
#define MUSB_RXCSR_H_WZC_BITS \
- ( MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
- | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY )
+ (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
+ | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
/* HUBADDR */
#define MUSB_HUBADDR_MULTI_TT 0x80