[ARM] pxa: simplify DMA register definitions

1. DRCMRxx is no longer recommended, use DRCMR(xx) instead, and
   pass DRCMR index by "struct resource" if possible

2. DCSRxx, DDADRxx, DSADRxx, DTADRxx, DCMDxx is never used, use
   DCSR(), DDADR(), DSADR(), DTADR(), DCMD() instead

Signed-off-by: Eric Miao <eric.miao@marvell.com>
Acked-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
index f842fd3d39a2338fb7072ae4646c41eb9610457c..4cac9269fdf2b208f0be45ddb735a7b03ae7fa4b 100644 (file)
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h
@@ -69,24 +69,6 @@
 /*
  * DMA Controller
  */
-
-#define DCSR0          __REG(0x40000000)  /* DMA Control / Status Register for Channel 0 */
-#define DCSR1          __REG(0x40000004)  /* DMA Control / Status Register for Channel 1 */
-#define DCSR2          __REG(0x40000008)  /* DMA Control / Status Register for Channel 2 */
-#define DCSR3          __REG(0x4000000c)  /* DMA Control / Status Register for Channel 3 */
-#define DCSR4          __REG(0x40000010)  /* DMA Control / Status Register for Channel 4 */
-#define DCSR5          __REG(0x40000014)  /* DMA Control / Status Register for Channel 5 */
-#define DCSR6          __REG(0x40000018)  /* DMA Control / Status Register for Channel 6 */
-#define DCSR7          __REG(0x4000001c)  /* DMA Control / Status Register for Channel 7 */
-#define DCSR8          __REG(0x40000020)  /* DMA Control / Status Register for Channel 8 */
-#define DCSR9          __REG(0x40000024)  /* DMA Control / Status Register for Channel 9 */
-#define DCSR10         __REG(0x40000028)  /* DMA Control / Status Register for Channel 10 */
-#define DCSR11         __REG(0x4000002c)  /* DMA Control / Status Register for Channel 11 */
-#define DCSR12         __REG(0x40000030)  /* DMA Control / Status Register for Channel 12 */
-#define DCSR13         __REG(0x40000034)  /* DMA Control / Status Register for Channel 13 */
-#define DCSR14         __REG(0x40000038)  /* DMA Control / Status Register for Channel 14 */
-#define DCSR15         __REG(0x4000003c)  /* DMA Control / Status Register for Channel 15 */
-
 #define DCSR(x)                __REG2(0x40000000, (x) << 2)
 
 #define DCSR_RUN       (1 << 31)       /* Run Bit (read / write) */
@@ -115,145 +97,9 @@
                        &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
                        &__REG2(0x40001100, ((n) & 0x3f) << 2)))
 
-#define DRCMR0         __REG(0x40000100)  /* Request to Channel Map Register for DREQ 0 */
-#define DRCMR1         __REG(0x40000104)  /* Request to Channel Map Register for DREQ 1 */
-#define DRCMR2         __REG(0x40000108)  /* Request to Channel Map Register for I2S receive Request */
-#define DRCMR3         __REG(0x4000010c)  /* Request to Channel Map Register for I2S transmit Request */
-#define DRCMR4         __REG(0x40000110)  /* Request to Channel Map Register for BTUART receive Request */
-#define DRCMR5         __REG(0x40000114)  /* Request to Channel Map Register for BTUART transmit Request. */
-#define DRCMR6         __REG(0x40000118)  /* Request to Channel Map Register for FFUART receive Request */
-#define DRCMR7         __REG(0x4000011c)  /* Request to Channel Map Register for FFUART transmit Request */
-#define DRCMR8         __REG(0x40000120)  /* Request to Channel Map Register for AC97 microphone Request */
-#define DRCMR9         __REG(0x40000124)  /* Request to Channel Map Register for AC97 modem receive Request */
-#define DRCMR10                __REG(0x40000128)  /* Request to Channel Map Register for AC97 modem transmit Request */
-#define DRCMR11                __REG(0x4000012c)  /* Request to Channel Map Register for AC97 audio receive Request */
-#define DRCMR12                __REG(0x40000130)  /* Request to Channel Map Register for AC97 audio transmit Request */
-#define DRCMR13                __REG(0x40000134)  /* Request to Channel Map Register for SSP receive Request */
-#define DRCMR14                __REG(0x40000138)  /* Request to Channel Map Register for SSP transmit Request */
-#define DRCMR15                __REG(0x4000013c)  /* Request to Channel Map Register for SSP2 receive Request */
-#define DRCMR16                __REG(0x40000140)  /* Request to Channel Map Register for SSP2 transmit Request */
-#define DRCMR17                __REG(0x40000144)  /* Request to Channel Map Register for ICP receive Request */
-#define DRCMR18                __REG(0x40000148)  /* Request to Channel Map Register for ICP transmit Request */
-#define DRCMR19                __REG(0x4000014c)  /* Request to Channel Map Register for STUART receive Request */
-#define DRCMR20                __REG(0x40000150)  /* Request to Channel Map Register for STUART transmit Request */
-#define DRCMR21                __REG(0x40000154)  /* Request to Channel Map Register for MMC receive Request */
-#define DRCMR22                __REG(0x40000158)  /* Request to Channel Map Register for MMC transmit Request */
-#define DRCMR23                __REG(0x4000015c)  /* Reserved */
-#define DRCMR24                __REG(0x40000160)  /* Reserved */
-#define DRCMR25                __REG(0x40000164)  /* Request to Channel Map Register for USB endpoint 1 Request */
-#define DRCMR26                __REG(0x40000168)  /* Request to Channel Map Register for USB endpoint 2 Request */
-#define DRCMR27                __REG(0x4000016C)  /* Request to Channel Map Register for USB endpoint 3 Request */
-#define DRCMR28                __REG(0x40000170)  /* Request to Channel Map Register for USB endpoint 4 Request */
-#define DRCMR29                __REG(0x40000174)  /* Reserved */
-#define DRCMR30                __REG(0x40000178)  /* Request to Channel Map Register for USB endpoint 6 Request */
-#define DRCMR31                __REG(0x4000017C)  /* Request to Channel Map Register for USB endpoint 7 Request */
-#define DRCMR32                __REG(0x40000180)  /* Request to Channel Map Register for USB endpoint 8 Request */
-#define DRCMR33                __REG(0x40000184)  /* Request to Channel Map Register for USB endpoint 9 Request */
-#define DRCMR34                __REG(0x40000188)  /* Reserved */
-#define DRCMR35                __REG(0x4000018C)  /* Request to Channel Map Register for USB endpoint 11 Request */
-#define DRCMR36                __REG(0x40000190)  /* Request to Channel Map Register for USB endpoint 12 Request */
-#define DRCMR37                __REG(0x40000194)  /* Request to Channel Map Register for USB endpoint 13 Request */
-#define DRCMR38                __REG(0x40000198)  /* Request to Channel Map Register for USB endpoint 14 Request */
-#define DRCMR39                __REG(0x4000019C)  /* Reserved */
-#define DRCMR66                __REG(0x40001108)  /* Request to Channel Map Register for SSP3 receive Request */
-#define DRCMR67                __REG(0x4000110C)  /* Request to Channel Map Register for SSP3 transmit Request */
-#define DRCMR68                __REG(0x40001110)  /* Request to Channel Map Register for Camera FIFO 0 Request */
-#define DRCMR69                __REG(0x40001114)  /* Request to Channel Map Register for Camera FIFO 1 Request */
-#define DRCMR70                __REG(0x40001118)  /* Request to Channel Map Register for Camera FIFO 2 Request */
-
-#define DRCMRRXSADR    DRCMR2
-#define DRCMRTXSADR    DRCMR3
-#define DRCMRRXBTRBR   DRCMR4
-#define DRCMRTXBTTHR   DRCMR5
-#define DRCMRRXFFRBR   DRCMR6
-#define DRCMRTXFFTHR   DRCMR7
-#define DRCMRRXMCDR    DRCMR8
-#define DRCMRRXMODR    DRCMR9
-#define DRCMRTXMODR    DRCMR10
-#define DRCMRRXPCDR    DRCMR11
-#define DRCMRTXPCDR    DRCMR12
-#define DRCMRRXSSDR    DRCMR13
-#define DRCMRTXSSDR    DRCMR14
-#define DRCMRRXSS2DR   DRCMR15
-#define DRCMRTXSS2DR   DRCMR16
-#define DRCMRRXICDR    DRCMR17
-#define DRCMRTXICDR    DRCMR18
-#define DRCMRRXSTRBR   DRCMR19
-#define DRCMRTXSTTHR   DRCMR20
-#define DRCMRRXMMC     DRCMR21
-#define DRCMRTXMMC     DRCMR22
-#define DRCMRRXSS3DR   DRCMR66
-#define DRCMRTXSS3DR   DRCMR67
-#define DRCMRUDC(x)    DRCMR((x) + 24)
-
 #define DRCMR_MAPVLD   (1 << 7)        /* Map Valid (read / write) */
 #define DRCMR_CHLNUM   0x1f            /* mask for Channel Number (read / write) */
 
-#define DDADR0         __REG(0x40000200)  /* DMA Descriptor Address Register Channel 0 */
-#define DSADR0         __REG(0x40000204)  /* DMA Source Address Register Channel 0 */
-#define DTADR0         __REG(0x40000208)  /* DMA Target Address Register Channel 0 */
-#define DCMD0          __REG(0x4000020c)  /* DMA Command Address Register Channel 0 */
-#define DDADR1         __REG(0x40000210)  /* DMA Descriptor Address Register Channel 1 */
-#define DSADR1         __REG(0x40000214)  /* DMA Source Address Register Channel 1 */
-#define DTADR1         __REG(0x40000218)  /* DMA Target Address Register Channel 1 */
-#define DCMD1          __REG(0x4000021c)  /* DMA Command Address Register Channel 1 */
-#define DDADR2         __REG(0x40000220)  /* DMA Descriptor Address Register Channel 2 */
-#define DSADR2         __REG(0x40000224)  /* DMA Source Address Register Channel 2 */
-#define DTADR2         __REG(0x40000228)  /* DMA Target Address Register Channel 2 */
-#define DCMD2          __REG(0x4000022c)  /* DMA Command Address Register Channel 2 */
-#define DDADR3         __REG(0x40000230)  /* DMA Descriptor Address Register Channel 3 */
-#define DSADR3         __REG(0x40000234)  /* DMA Source Address Register Channel 3 */
-#define DTADR3         __REG(0x40000238)  /* DMA Target Address Register Channel 3 */
-#define DCMD3          __REG(0x4000023c)  /* DMA Command Address Register Channel 3 */
-#define DDADR4         __REG(0x40000240)  /* DMA Descriptor Address Register Channel 4 */
-#define DSADR4         __REG(0x40000244)  /* DMA Source Address Register Channel 4 */
-#define DTADR4         __REG(0x40000248)  /* DMA Target Address Register Channel 4 */
-#define DCMD4          __REG(0x4000024c)  /* DMA Command Address Register Channel 4 */
-#define DDADR5         __REG(0x40000250)  /* DMA Descriptor Address Register Channel 5 */
-#define DSADR5         __REG(0x40000254)  /* DMA Source Address Register Channel 5 */
-#define DTADR5         __REG(0x40000258)  /* DMA Target Address Register Channel 5 */
-#define DCMD5          __REG(0x4000025c)  /* DMA Command Address Register Channel 5 */
-#define DDADR6         __REG(0x40000260)  /* DMA Descriptor Address Register Channel 6 */
-#define DSADR6         __REG(0x40000264)  /* DMA Source Address Register Channel 6 */
-#define DTADR6         __REG(0x40000268)  /* DMA Target Address Register Channel 6 */
-#define DCMD6          __REG(0x4000026c)  /* DMA Command Address Register Channel 6 */
-#define DDADR7         __REG(0x40000270)  /* DMA Descriptor Address Register Channel 7 */
-#define DSADR7         __REG(0x40000274)  /* DMA Source Address Register Channel 7 */
-#define DTADR7         __REG(0x40000278)  /* DMA Target Address Register Channel 7 */
-#define DCMD7          __REG(0x4000027c)  /* DMA Command Address Register Channel 7 */
-#define DDADR8         __REG(0x40000280)  /* DMA Descriptor Address Register Channel 8 */
-#define DSADR8         __REG(0x40000284)  /* DMA Source Address Register Channel 8 */
-#define DTADR8         __REG(0x40000288)  /* DMA Target Address Register Channel 8 */
-#define DCMD8          __REG(0x4000028c)  /* DMA Command Address Register Channel 8 */
-#define DDADR9         __REG(0x40000290)  /* DMA Descriptor Address Register Channel 9 */
-#define DSADR9         __REG(0x40000294)  /* DMA Source Address Register Channel 9 */
-#define DTADR9         __REG(0x40000298)  /* DMA Target Address Register Channel 9 */
-#define DCMD9          __REG(0x4000029c)  /* DMA Command Address Register Channel 9 */
-#define DDADR10                __REG(0x400002a0)  /* DMA Descriptor Address Register Channel 10 */
-#define DSADR10                __REG(0x400002a4)  /* DMA Source Address Register Channel 10 */
-#define DTADR10                __REG(0x400002a8)  /* DMA Target Address Register Channel 10 */
-#define DCMD10         __REG(0x400002ac)  /* DMA Command Address Register Channel 10 */
-#define DDADR11                __REG(0x400002b0)  /* DMA Descriptor Address Register Channel 11 */
-#define DSADR11                __REG(0x400002b4)  /* DMA Source Address Register Channel 11 */
-#define DTADR11                __REG(0x400002b8)  /* DMA Target Address Register Channel 11 */
-#define DCMD11         __REG(0x400002bc)  /* DMA Command Address Register Channel 11 */
-#define DDADR12                __REG(0x400002c0)  /* DMA Descriptor Address Register Channel 12 */
-#define DSADR12                __REG(0x400002c4)  /* DMA Source Address Register Channel 12 */
-#define DTADR12                __REG(0x400002c8)  /* DMA Target Address Register Channel 12 */
-#define DCMD12         __REG(0x400002cc)  /* DMA Command Address Register Channel 12 */
-#define DDADR13                __REG(0x400002d0)  /* DMA Descriptor Address Register Channel 13 */
-#define DSADR13                __REG(0x400002d4)  /* DMA Source Address Register Channel 13 */
-#define DTADR13                __REG(0x400002d8)  /* DMA Target Address Register Channel 13 */
-#define DCMD13         __REG(0x400002dc)  /* DMA Command Address Register Channel 13 */
-#define DDADR14                __REG(0x400002e0)  /* DMA Descriptor Address Register Channel 14 */
-#define DSADR14                __REG(0x400002e4)  /* DMA Source Address Register Channel 14 */
-#define DTADR14                __REG(0x400002e8)  /* DMA Target Address Register Channel 14 */
-#define DCMD14         __REG(0x400002ec)  /* DMA Command Address Register Channel 14 */
-#define DDADR15                __REG(0x400002f0)  /* DMA Descriptor Address Register Channel 15 */
-#define DSADR15                __REG(0x400002f4)  /* DMA Source Address Register Channel 15 */
-#define DTADR15                __REG(0x400002f8)  /* DMA Target Address Register Channel 15 */
-#define DCMD15         __REG(0x400002fc)  /* DMA Command Address Register Channel 15 */
-
 #define DDADR(x)       __REG2(0x40000200, (x) << 4)
 #define DSADR(x)       __REG2(0x40000204, (x) << 4)
 #define DTADR(x)       __REG2(0x40000208, (x) << 4)

diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index 388cf94055d35e13311569fb29494ce949d0e0c2..cf96b2cc4f1c4b70f59ef279ad8cfee8b4535f1a 100644 (file)
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -1025,9 +1025,9 @@ static int pxa_camera_resume(struct soc_camera_device *icd)
        struct pxa_camera_dev *pcdev = ici->priv;
        int i = 0, ret = 0;
 
-       DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD;
-       DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD;
-       DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD;
+       DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
+       DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
+       DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
 
        CICR0 = pcdev->save_cicr[i++] & ~CICR0_ENB;
        CICR1 = pcdev->save_cicr[i++];
@@ -1171,9 +1171,9 @@ static int pxa_camera_probe(struct platform_device *pdev)
        }
        dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
 
-       DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD;
-       DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD;
-       DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD;
+       DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
+       DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
+       DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
 
        /* request irq */
        err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,

diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index 4aa61a1a3d55f7cccc10003bc3a1bbc2f463a790..c5b02b66f7560a570210f075e6d72eda219e97df 100644 (file)
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -572,8 +572,8 @@ static void pxa_irda_startup(struct pxa_irda *si)
        ICCR2 = ICCR2_TXP | ICCR2_TRIG_32;
 
        /* configure DMAC */
-       DRCMR17 = si->rxdma | DRCMR_MAPVLD;
-       DRCMR18 = si->txdma | DRCMR_MAPVLD;
+       DRCMR(17) = si->rxdma | DRCMR_MAPVLD;
+       DRCMR(18) = si->txdma | DRCMR_MAPVLD;
 
        /* force SIR reinitialization */
        si->speed = 4000000;
@@ -602,8 +602,8 @@ static void pxa_irda_shutdown(struct pxa_irda *si)
        /* disable the STUART or FICP clocks */
        pxa_irda_disable_clk(si);
 
-       DRCMR17 = 0;
-       DRCMR18 = 0;
+       DRCMR(17) = 0;
+       DRCMR(18) = 0;
 
        local_irq_restore(flags);
 

diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c
index 199cca3366df244b4fd05c5125ac096a0ade0f73..714b3baa4be776ddcec323e4871cdbec0c6be44a 100644 (file)
--- a/sound/arm/pxa2xx-ac97.c
+++ b/sound/arm/pxa2xx-ac97.c
@@ -215,7 +215,7 @@ static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
        .name                   = "AC97 PCM out",
        .dev_addr               = __PREG(PCDR),
-       .drcmr                  = &DRCMRTXPCDR,
+       .drcmr                  = &DRCMR(12),
        .dcmd                   = DCMD_INCSRCADDR | DCMD_FLOWTRG |
                                  DCMD_BURST32 | DCMD_WIDTH4,
 };
@@ -223,7 +223,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_in = {
        .name                   = "AC97 PCM in",
        .dev_addr               = __PREG(PCDR),
-       .drcmr                  = &DRCMRRXPCDR,
+       .drcmr                  = &DRCMR(11),
        .dcmd                   = DCMD_INCTRGADDR | DCMD_FLOWSRC |
                                  DCMD_BURST32 | DCMD_WIDTH4,
 };

diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c
index 7d7ce1648361f58bb78cfa3d7a47ea090d004ca4..ac8f227bab0be806307b6cc0cbcaa22af6647f2b 100644 (file)
--- a/sound/soc/pxa/pxa2xx-ac97.c
+++ b/sound/soc/pxa/pxa2xx-ac97.c
@@ -244,7 +244,7 @@ struct snd_ac97_bus_ops soc_ac97_ops = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = {
        .name                   = "AC97 PCM Stereo out",
        .dev_addr               = __PREG(PCDR),
-       .drcmr                  = &DRCMRTXPCDR,
+       .drcmr                  = &DRCMR(12),
        .dcmd                   = DCMD_INCSRCADDR | DCMD_FLOWTRG |
                                  DCMD_BURST32 | DCMD_WIDTH4,
 };
@@ -252,7 +252,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = {
        .name                   = "AC97 PCM Stereo in",
        .dev_addr               = __PREG(PCDR),
-       .drcmr                  = &DRCMRRXPCDR,
+       .drcmr                  = &DRCMR(11),
        .dcmd                   = DCMD_INCTRGADDR | DCMD_FLOWSRC |
                                  DCMD_BURST32 | DCMD_WIDTH4,
 };
@@ -260,7 +260,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = {
        .name                   = "AC97 Aux PCM (Slot 5) Mono out",
        .dev_addr               = __PREG(MODR),
-       .drcmr                  = &DRCMRTXMODR,
+       .drcmr                  = &DRCMR(10),
        .dcmd                   = DCMD_INCSRCADDR | DCMD_FLOWTRG |
                                  DCMD_BURST16 | DCMD_WIDTH2,
 };
@@ -268,7 +268,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = {
        .name                   = "AC97 Aux PCM (Slot 5) Mono in",
        .dev_addr               = __PREG(MODR),
-       .drcmr                  = &DRCMRRXMODR,
+       .drcmr                  = &DRCMR(9),
        .dcmd                   = DCMD_INCTRGADDR | DCMD_FLOWSRC |
                                  DCMD_BURST16 | DCMD_WIDTH2,
 };
@@ -276,7 +276,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = {
        .name                   = "AC97 Mic PCM (Slot 6) Mono in",
        .dev_addr               = __PREG(MCDR),
-       .drcmr                  = &DRCMRRXMCDR,
+       .drcmr                  = &DRCMR(8),
        .dcmd                   = DCMD_INCTRGADDR | DCMD_FLOWSRC |
                                  DCMD_BURST16 | DCMD_WIDTH2,
 };

diff --git a/sound/soc/pxa/pxa2xx-i2s.c b/sound/soc/pxa/pxa2xx-i2s.c
index c796b1882776308390fa10e4225ff26820aaa9db..2dbe612fdddc8abb5b267d532d0d7c187265c30e 100644 (file)
--- a/sound/soc/pxa/pxa2xx-i2s.c
+++ b/sound/soc/pxa/pxa2xx-i2s.c
@@ -44,7 +44,7 @@ static struct clk *clk_i2s;
 static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
        .name                   = "I2S PCM Stereo out",
        .dev_addr               = __PREG(SADR),
-       .drcmr                  = &DRCMRTXSADR,
+       .drcmr                  = &DRCMR(3),
        .dcmd                   = DCMD_INCSRCADDR | DCMD_FLOWTRG |
                                  DCMD_BURST32 | DCMD_WIDTH4,
 };
@@ -52,7 +52,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
 static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
        .name                   = "I2S PCM Stereo in",
        .dev_addr               = __PREG(SADR),
-       .drcmr                  = &DRCMRRXSADR,
+       .drcmr                  = &DRCMR(2),
        .dcmd                   = DCMD_INCTRGADDR | DCMD_FLOWSRC |
                                  DCMD_BURST32 | DCMD_WIDTH4,
 };