[PATCH] x86-64: x86-64 add Intel Core related PMU MSRs definitions

Add o the x86-64 tree a bunch of MSRs related to performance
monitoring for the processors based on Intel Core microarchitecture.
It also adds some architectural MSRs for PEBS. A similar patch for i386 will
follow.

changelog:
	- add Intel Precise-Event Based sampling (PEBS) related MSR
	- add Intel Data Save (DS) Area related MSR
	- add Intel Core microarchitecure performance counter MSRs

Signed-off-by: stephane eranian <eranian@hpl.hp.com>
Signed-off-by: Andi Kleen <ak@suse.de>

diff --git a/include/asm-x86_64/msr.h b/include/asm-x86_64/msr.h
index 37e194169fac2f2793894331eb9ec34d81401dfa..a745c5008a6017e0fd9ad1b36a444fb33711d032 100644 (file)
--- a/include/asm-x86_64/msr.h
+++ b/include/asm-x86_64/msr.h
@@ -210,6 +210,10 @@ static inline unsigned int cpuid_edx(unsigned int op)
 #define MSR_IA32_LASTINTFROMIP     0x1dd
 #define MSR_IA32_LASTINTTOIP       0x1de
 
+#define MSR_IA32_PEBS_ENABLE           0x3f1
+#define MSR_IA32_DS_AREA               0x600
+#define MSR_IA32_PERF_CAPABILITIES     0x345
+
 #define MSR_MTRRfix64K_00000   0x250
 #define MSR_MTRRfix16K_80000   0x258
 #define MSR_MTRRfix16K_A0000   0x259
@@ -407,4 +411,13 @@ static inline unsigned int cpuid_edx(unsigned int op)
 #define MSR_P4_U2L_ESCR0               0x3b0
 #define MSR_P4_U2L_ESCR1               0x3b1
 
+/* Intel Core-based CPU performance counters */
+#define MSR_CORE_PERF_FIXED_CTR0       0x309
+#define MSR_CORE_PERF_FIXED_CTR1       0x30a
+#define MSR_CORE_PERF_FIXED_CTR2       0x30b
+#define MSR_CORE_PERF_FIXED_CTR_CTRL   0x38d
+#define MSR_CORE_PERF_GLOBAL_STATUS    0x38e
+#define MSR_CORE_PERF_GLOBAL_CTRL      0x38f
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL  0x390
+
 #endif