#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
-#define OMAP34XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
-#define OMAP34XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
-#define OMAP34XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
-#define OMAP34XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
#define INT_34XX_USIM_IRQ 35
#define INT_34XX_WDT3_IRQ 36
#define INT_34XX_SPI4_IRQ 48
-#define INT_34XX_MCBSP1_IRQ_TX 59
-#define INT_34XX_MCBSP1_IRQ_RX 60
#define INT_34XX_I2C3_IRQ 61
-#define INT_34XX_MCBSP2_IRQ_TX 62
-#define INT_34XX_MCBSP2_IRQ_RX 63
#define INT_34XX_PBIAS_IRQ 75
#define INT_34XX_OHCI_IRQ 76
#define INT_34XX_EHCI_IRQ 77