OMAP2/3 clock: use clk->prcm_mod for all struct clk register addressing

Use the clk->prcm_mod field for all register addresses in struct clk.
Remove all usage of the *_REGADDR() and *_OFFSET() macros from the
clock tree.  This eliminates a set of (__force void __iomem *) casts
and removes all of the OMAP2xxx register address rewriting.  Shrink
the width of the enable_reg/clksel_reg registers to 16 bits, saving 4
bytes per struct clk.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 621babcf91234aca17a2028a020534757cbb595f..1effb34f62c580ca1e60f17a8e1170720d49440a 100644 (file)
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -160,7 +160,8 @@ void omap2_init_clksel_parent(struct clk *clk)
        if (!clk->clksel)
                return;
 
-       r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+       r = _omap2_clk_read_reg(clk->clksel_reg, clk);
+       r &= clk->clksel_mask;
        r >>= __ffs(clk->clksel_mask);
 
        for (clks = clk->clksel; clks->parent && !found; clks++) {
@@ -211,7 +212,8 @@ u32 omap2_get_dpll_rate(struct clk *clk)
                return 0;
 
        /* Return bypass rate if DPLL is bypassed */
-       v = __raw_readl(dd->idlest_reg) & dd->idlest_mask;
+       v = cm_read_mod_reg(clk->prcm_mod, dd->idlest_reg);
+       v &= dd->idlest_mask;
        v >>= __ffs(dd->idlest_mask);
        if (cpu_is_omap24xx()) {
 
@@ -227,7 +229,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
 
        }
 
-       v = __raw_readl(dd->mult_div1_reg);
+       v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
        dpll_mult = v & dd->mult_mask;
        dpll_mult >>= __ffs(dd->mult_mask);
        dpll_div = v & dd->div1_mask;
@@ -302,23 +304,20 @@ int omap2_wait_clock_ready(s16 prcm_mod, u16 reg_index, u32 mask,
  */
 static void omap2_clk_wait_ready(struct clk *clk)
 {
+       u16 other_reg, idlest_reg;
        u32 other_bit, idlest_bit;
-       unsigned long reg, other_reg, idlest_reg, prcm_regid;
 
        /* Only CM-controlled clocks affect module IDLEST */
        if (clk->prcm_mod & ~PRCM_MOD_ADDR_MASK)
                return;
 
-       reg = (unsigned long)clk->enable_reg;
-       prcm_regid = reg & 0xff;
+       other_reg = clk->enable_reg & ~PRCM_REGTYPE_MASK;
 
-       other_reg = reg & ~PRCM_REGTYPE_MASK;
-
-       /* If we are enabling an fclk, also test the iclk; and vice versa */
-       if (prcm_regid >= CM_FCLKEN1 && prcm_regid <= OMAP24XX_CM_FCLKEN2)
-               other_reg |= CM_ICLKEN_REGTYPE;
-       else
+       /* If we are enabling an iclk, also test the fclk; and vice versa */
+       if (clk->enable_reg & CM_ICLKEN_REGTYPE)
                other_reg |= CM_FCLKEN_REGTYPE;
+       else
+               other_reg |= CM_ICLKEN_REGTYPE;
 
        /* Covers most of the cases - a few exceptions are below */
        other_bit = 1 << clk->enable_bit;
@@ -326,7 +325,7 @@ static void omap2_clk_wait_ready(struct clk *clk)
 
        /* 24xx: DSS and CAM have no idlest bits for their target agents */
        if (cpu_is_omap24xx() && clk->prcm_mod == CORE_MOD &&
-           (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
+           (clk->enable_reg == CM_FCLKEN1 || clk->enable_reg == CM_ICLKEN1)) {
 
                if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
                    clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
@@ -340,7 +339,8 @@ static void omap2_clk_wait_ready(struct clk *clk)
 
                /* SSI */
                if (clk->prcm_mod == CORE_MOD &&
-                   (reg & 0x0f) == 0 &&
+                   (clk->enable_reg == CM_FCLKEN1 ||
+                    clk->enable_reg == CM_ICLKEN1) &&
                    clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
 
                        if (system_rev == OMAP3430_REV_ES1_0)
@@ -382,16 +382,13 @@ static void omap2_clk_wait_ready(struct clk *clk)
                }
        }
 
-       /* Check if both functional and interface clocks
-        * are running. */
-       if (!(__raw_readl((void __iomem *)other_reg) & other_bit))
+       /* Check if both functional and interface clocks are running. */
+       if (!(cm_read_mod_reg(clk->prcm_mod, other_reg) & other_bit))
                return;
 
        idlest_reg = other_reg & ~PRCM_REGTYPE_MASK;
        idlest_reg |= CM_IDLEST_REGTYPE;
 
-       idlest_reg &= 0xff; /* convert to PRCM register index */
-
        omap2_wait_clock_ready(clk->prcm_mod, idlest_reg, idlest_bit,
                               clk->name);
 }
@@ -409,18 +406,12 @@ static int _omap2_clk_enable(struct clk *clk)
        if (clk->enable)
                return clk->enable(clk);
 
-       if (unlikely(clk->enable_reg == NULL)) {
-               printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
-                      clk->name);
-               return 0; /* REVISIT: -EINVAL */
-       }
-
-       v = __raw_readl(clk->enable_reg);
+       v = _omap2_clk_read_reg(clk->enable_reg, clk);
        if (clk->flags & INVERT_ENABLE)
                v &= ~(1 << clk->enable_bit);
        else
                v |= (1 << clk->enable_bit);
-       __raw_writel(v, clk->enable_reg);
+       _omap2_clk_write_reg(v, clk->enable_reg, clk);
        wmb();
 
        omap2_clk_wait_ready(clk);
@@ -441,22 +432,12 @@ static void _omap2_clk_disable(struct clk *clk)
                return;
        }
 
-       if (clk->enable_reg == NULL) {
-               /*
-                * 'Independent' here refers to a clock which is not
-                * controlled by its parent.
-                */
-               printk(KERN_ERR "clock: clk_disable called on independent "
-                      "clock %s which has no enable_reg\n", clk->name);
-               return;
-       }
-
-       v = __raw_readl(clk->enable_reg);
+       v = _omap2_clk_read_reg(clk->enable_reg, clk);
        if (clk->flags & INVERT_ENABLE)
                v |= (1 << clk->enable_bit);
        else
                v &= ~(1 << clk->enable_bit);
-       __raw_writel(v, clk->enable_reg);
+       _omap2_clk_write_reg(v, clk->enable_reg, clk);
        wmb();
 }
 
@@ -739,7 +720,8 @@ u32 omap2_clksel_get_divisor(struct clk *clk)
        if (!clk->clksel_mask)
                return 0;
 
-       v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+       v = _omap2_clk_read_reg(clk->clksel_reg, clk);
+       v &= clk->clksel_mask;
        v >>= __ffs(clk->clksel_mask);
 
        return omap2_clksel_to_divisor(clk, v);
@@ -754,16 +736,16 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 
        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
        if (validrate != rate)
-               return -EINVAL;
+              return -EINVAL;
 
        field_val = omap2_divisor_to_clksel(clk, new_div);
        if (field_val == ~0)
                return -EINVAL;
 
-       v = __raw_readl(clk->clksel_reg);
+       v = _omap2_clk_read_reg(clk->clksel_reg, clk);
        v &= ~clk->clksel_mask;
        v |= field_val << __ffs(clk->clksel_mask);
-       __raw_writel(v, clk->clksel_reg);
+       _omap2_clk_write_reg(v, clk->clksel_reg, clk);
 
        wmb();
 
@@ -853,10 +835,10 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
                _omap2_clk_disable(clk);
 
        /* Set new source value (previous dividers if any in effect) */
-       v = __raw_readl(clk->clksel_reg);
+       v = _omap2_clk_read_reg(clk->clksel_reg, clk);
        v &= ~clk->clksel_mask;
        v |= field_val << __ffs(clk->clksel_mask);
-       __raw_writel(v, clk->clksel_reg);
+       _omap2_clk_write_reg(v, clk->clksel_reg, clk);
        wmb();
 
        if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
@@ -1075,7 +1057,7 @@ void omap2_clk_disable_unused(struct clk *clk)
 
        v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
 
-       regval32 = __raw_readl(clk->enable_reg);
+       regval32 = _omap2_clk_read_reg(clk->enable_reg, clk);
        if ((regval32 & (1 << clk->enable_bit)) == v)
                return;
 

diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index a97d89d470aea20670f1343b98eb0ccc6cc195fe..a54f10f92cd436bbd504301976d288abacb978b6 100644 (file)
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -201,7 +201,8 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
                if (!dd)
                        goto dpll_exit;
 
-               tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
+               tmpset.cm_clksel1_pll = cm_read_mod_reg(clk->prcm_mod,
+                                                       dd->mult_div1_reg);
                tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
                                           dd->div1_mask);
                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
@@ -500,39 +501,6 @@ static int __init omap2_clk_arch_init(void)
 }
 arch_initcall(omap2_clk_arch_init);
 
-static u32 prm_base;
-static u32 cm_base;
-
-/*
- * Since we share clock data for 242x and 243x, we need to rewrite some
- * some register base offsets. Assume offset is at prm_base if flagged,
- * else assume it's cm_base.
- */
-static inline void omap2_clk_check_reg(u32 flags, void __iomem **reg)
-{
-       u32 tmp = (__force u32)*reg;
-
-       if ((tmp >> 24) != 0)
-               return;
-
-       if (flags & OFFSET_GR_MOD)
-               tmp += prm_base;
-       else
-               tmp += cm_base;
-
-       *reg = (__force void __iomem *)tmp;
-}
-
-static void __init omap2_clk_rewrite_base(struct clk *clk)
-{
-       omap2_clk_check_reg(clk->flags, &clk->clksel_reg);
-       omap2_clk_check_reg(clk->flags, &clk->enable_reg);
-       if (clk->dpll_data) {
-               omap2_clk_check_reg(0, &clk->dpll_data->mult_div1_reg);
-               omap2_clk_check_reg(0, &clk->dpll_data->idlest_reg);
-       }
-}
-
 int __init omap2_clk_init(void)
 {
        struct prcm_config *prcm;
@@ -544,12 +512,6 @@ int __init omap2_clk_init(void)
        else if (cpu_is_omap2430())
                cpu_mask = RATE_IN_243X;
 
-       for (clkp = onchip_24xx_clks;
-            clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
-            clkp++) {
-                       omap2_clk_rewrite_base(*clkp);
-       }
-
        clk_init(&omap2_clk_functions);
 
        omap2_osc_clk_recalc(&osc_ck);
@@ -603,9 +565,3 @@ int __init omap2_clk_init(void)
 
        return 0;
 }
-
-void __init omap2_set_globals_clock24xx(struct omap_globals *omap2_globals)
-{
-       prm_base = (__force u32)omap2_globals->prm;
-       cm_base = (__force u32)omap2_globals->cm;
-}

diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index e4630e532883efd7e75f5955a2029042ed864227..41f9e2cedbe2bb0e1ef8fbf94b548282a01d2fa5 100644 (file)
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -600,15 +600,6 @@ static struct prcm_config rate_table[] = {
        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 };
 
-/*
- * Since 2420 and 2430 have different cm_base, we use offsets only here.
- * Clock code will rewrite the register address as needed.
- */
-#define _CM_REG_OFFSET(module, reg)                            \
-                       ((__force void __iomem *)(module) + (reg))
-#define _GR_MOD_OFFSET(reg)                                    \
-                       ((__force void __iomem *)(OMAP24XX_GR_MOD + (reg)))
-
 /*-------------------------------------------------------------------------
  * 24xx clock tree.
  *
@@ -679,10 +670,10 @@ static struct clk alt_ck = {              /* Typical 54M or 48M, may not exist */
  */
 
 static struct dpll_data dpll_dd = {
-       .mult_div1_reg          = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
+       .mult_div1_reg          = CM_CLKSEL1,
        .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
        .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
-       .idlest_reg             = _CM_REG_OFFSET(PLL_MOD, CM_IDLEST),
+       .idlest_reg             = CM_IDLEST,
        .idlest_mask            = OMAP24XX_ST_CORE_CLK_MASK,
        .max_multiplier         = 1024,
        .max_divider            = 16,
@@ -713,7 +704,7 @@ static struct clk apll96_ck = {
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
        .clkdm          = { .name = "prm_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
        .enable         = &omap2_clk_fixed_enable,
        .disable        = &omap2_clk_fixed_disable,
@@ -728,7 +719,7 @@ static struct clk apll54_ck = {
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
        .clkdm          = { .name = "prm_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
        .enable         = &omap2_clk_fixed_enable,
        .disable        = &omap2_clk_fixed_disable,
@@ -765,7 +756,7 @@ static struct clk func_54m_ck = {
                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "cm_clkdm" },
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP24XX_54M_SOURCE,
        .clksel         = func_54m_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -806,7 +797,7 @@ static struct clk func_96m_ck = {
                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "cm_clkdm" },
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP2430_96M_SOURCE,
        .clksel         = func_96m_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -840,7 +831,7 @@ static struct clk func_48m_ck = {
                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "cm_clkdm" },
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP24XX_48M_SOURCE,
        .clksel         = func_48m_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -908,12 +899,12 @@ static struct clk sys_clkout_src = {
        .parent         = &func_54m_ck,
        .prcm_mod       = OMAP24XX_GR_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_PROPAGATES | OFFSET_GR_MOD,
+                               RATE_PROPAGATES,
        .clkdm          = { .name = "prm_clkdm" },
-       .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
+       .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
        .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
+       .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
        .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
        .clksel         = common_clkout_src_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -940,9 +931,9 @@ static struct clk sys_clkout = {
        .parent         = &sys_clkout_src,
        .prcm_mod       = OMAP24XX_GR_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD,
+                               PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "prm_clkdm" },
-       .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
+       .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
        .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
        .clksel         = sys_clkout_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -955,12 +946,12 @@ static struct clk sys_clkout2_src = {
        .name           = "sys_clkout2_src",
        .parent         = &func_54m_ck,
        .prcm_mod       = OMAP24XX_GR_MOD,
-       .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD,
+       .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
        .clkdm          = { .name = "cm_clkdm" },
-       .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
+       .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
        .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
+       .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
        .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
        .clksel         = common_clkout_src_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -978,10 +969,9 @@ static struct clk sys_clkout2 = {
        .name           = "sys_clkout2",
        .parent         = &sys_clkout2_src,
        .prcm_mod       = OMAP24XX_GR_MOD,
-       .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK |
-                               OFFSET_GR_MOD,
+       .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "cm_clkdm" },
-       .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
+       .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
        .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
        .clksel         = sys_clkout2_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -993,9 +983,9 @@ static struct clk emul_ck = {
        .name           = "emul_ck",
        .parent         = &func_54m_ck,
        .prcm_mod       = OMAP24XX_GR_MOD,
-       .flags          = CLOCK_IN_OMAP242X | OFFSET_GR_MOD,
+       .flags          = CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "cm_clkdm" },
-       .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET),
+       .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET,
        .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
        .recalc         = &followparent_recalc,
 
@@ -1034,7 +1024,7 @@ static struct clk mpu_ck = {      /* Control cpu */
                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
        .clkdm          = { .name = "mpu_clkdm" },
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(MPU_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
        .clksel         = mpu_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1076,9 +1066,9 @@ static struct clk dsp_fck = {
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
        .clkdm          = { .name = "dsp_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
-       .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
        .clksel         = dsp_fck_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1107,7 +1097,7 @@ static struct clk dsp_irate_ick = {
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
                                CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dsp_clkdm" },
-       .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
        .clksel         = dsp_irate_ick_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1122,7 +1112,7 @@ static struct clk dsp_ick = {
        .prcm_mod       = OMAP24XX_DSP_MOD,
        .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
        .clkdm          = { .name = "dsp_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
 };
 
@@ -1133,7 +1123,7 @@ static struct clk iva2_1_ick = {
        .prcm_mod       = OMAP24XX_DSP_MOD,
        .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
        .clkdm          = { .name = "dsp_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 };
 
@@ -1149,9 +1139,9 @@ static struct clk iva1_ifck = {
        .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
                                RATE_PROPAGATES | DELAYED_APP,
        .clkdm          = { .name = "iva1_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
-       .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
        .clksel         = dsp_fck_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1166,7 +1156,7 @@ static struct clk iva1_mpu_int_ifck = {
        .prcm_mod       = OMAP24XX_DSP_MOD,
        .flags          = CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "iva1_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
        .fixed_div      = 2,
        .recalc         = &omap2_fixed_divisor_recalc,
@@ -1215,7 +1205,7 @@ static struct clk core_l3_ck = {  /* Used for ick and fck, interconnect */
                                ALWAYS_ENABLED | DELAYED_APP |
                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
        .clkdm          = { .name = "core_l3_clkdm" },
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
        .clksel         = core_l3_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1244,9 +1234,9 @@ static struct clk usb_l4_ick = {  /* FS-USB interface clock */
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                DELAYED_APP | CONFIG_PARTICIPANT,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
        .clksel         = usb_l4_ick_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1279,7 +1269,7 @@ static struct clk l4_ck = {               /* used both as an ick and fck */
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
        .clksel         = l4_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1318,9 +1308,9 @@ static struct clk ssi_ssr_sst_fck = {
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                DELAYED_APP,
        .clkdm          = { .name = "core_l3_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
        .clksel         = ssi_ssr_sst_fck_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1338,7 +1328,7 @@ static struct clk ssi_l4_ick = {
        .prcm_mod       = CORE_MOD,
        .clkdm          = { .name = "core_l4_clkdm" },
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1369,9 +1359,9 @@ static struct clk gfx_3d_fck = {
        .prcm_mod       = GFX_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "gfx_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP24XX_EN_3D_SHIFT,
-       .clksel_reg     = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
        .clksel         = gfx_fck_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1385,9 +1375,9 @@ static struct clk gfx_2d_fck = {
        .prcm_mod       = GFX_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "gfx_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP24XX_EN_2D_SHIFT,
-       .clksel_reg     = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
        .clksel         = gfx_fck_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1401,7 +1391,7 @@ static struct clk gfx_ick = {
        .prcm_mod       = GFX_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "gfx_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP_EN_GFX_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1432,9 +1422,9 @@ static struct clk mdm_ick = {             /* used both as a ick and fck */
        .prcm_mod       = OMAP2430_MDM_MOD,
        .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
        .clkdm          = { .name = "mdm_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
-       .clksel_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
        .clksel         = mdm_ick_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1448,7 +1438,7 @@ static struct clk mdm_osc_ck = {
        .prcm_mod       = OMAP2430_MDM_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "mdm_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP2430_EN_OSC_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1494,7 +1484,7 @@ static struct clk dss_ick = {             /* Enables both L3,L4 ICLK's */
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "dss_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1506,10 +1496,10 @@ static struct clk dss1_fck = {
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                DELAYED_APP,
        .clkdm          = { .name = "dss_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
        .clksel         = dss1_fck_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1540,10 +1530,10 @@ static struct clk dss2_fck = {          /* Alt clk used in power management */
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                DELAYED_APP,
        .clkdm          = { .name = "dss_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
        .clksel         = dss2_fck_clksel,
        .recalc         = &followparent_recalc,
@@ -1555,7 +1545,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "dss_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_TV_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1584,7 +1574,7 @@ static struct clk gpt1_ick = {
        .prcm_mod       = WKUP_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1595,10 +1585,10 @@ static struct clk gpt1_fck = {
        .prcm_mod       = WKUP_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
        .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1612,7 +1602,7 @@ static struct clk gpt2_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1623,10 +1613,10 @@ static struct clk gpt2_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+       .clksel_reg     = CM_CLKSEL2,
        .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
        .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1638,7 +1628,7 @@ static struct clk gpt3_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1649,10 +1639,10 @@ static struct clk gpt3_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+       .clksel_reg     = CM_CLKSEL2,
        .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
        .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1664,7 +1654,7 @@ static struct clk gpt4_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1675,10 +1665,10 @@ static struct clk gpt4_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+       .clksel_reg     = CM_CLKSEL2,
        .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
        .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1690,7 +1680,7 @@ static struct clk gpt5_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1701,10 +1691,10 @@ static struct clk gpt5_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+       .clksel_reg     = CM_CLKSEL2,
        .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
        .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1716,7 +1706,7 @@ static struct clk gpt6_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1727,10 +1717,10 @@ static struct clk gpt6_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+       .clksel_reg     = CM_CLKSEL2,
        .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
        .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1742,7 +1732,7 @@ static struct clk gpt7_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1753,10 +1743,10 @@ static struct clk gpt7_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+       .clksel_reg     = CM_CLKSEL2,
        .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
        .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1768,7 +1758,7 @@ static struct clk gpt8_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1779,10 +1769,10 @@ static struct clk gpt8_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+       .clksel_reg     = CM_CLKSEL2,
        .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
        .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1794,7 +1784,7 @@ static struct clk gpt9_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1805,10 +1795,10 @@ static struct clk gpt9_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+       .clksel_reg     = CM_CLKSEL2,
        .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
        .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1820,7 +1810,7 @@ static struct clk gpt10_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1831,10 +1821,10 @@ static struct clk gpt10_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+       .clksel_reg     = CM_CLKSEL2,
        .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
        .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1846,7 +1836,7 @@ static struct clk gpt11_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1857,10 +1847,10 @@ static struct clk gpt11_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+       .clksel_reg     = CM_CLKSEL2,
        .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
        .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1872,7 +1862,7 @@ static struct clk gpt12_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1883,10 +1873,10 @@ static struct clk gpt12_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
+       .clksel_reg     = CM_CLKSEL2,
        .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
        .clksel         = omap24xx_gpt_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -1899,7 +1889,7 @@ static struct clk mcbsp1_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1911,7 +1901,7 @@ static struct clk mcbsp1_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1923,7 +1913,7 @@ static struct clk mcbsp2_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1935,7 +1925,7 @@ static struct clk mcbsp2_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1947,7 +1937,7 @@ static struct clk mcbsp3_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1959,7 +1949,7 @@ static struct clk mcbsp3_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1971,7 +1961,7 @@ static struct clk mcbsp4_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1983,7 +1973,7 @@ static struct clk mcbsp4_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -1995,7 +1985,7 @@ static struct clk mcbsp5_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2007,7 +1997,7 @@ static struct clk mcbsp5_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2019,7 +2009,7 @@ static struct clk mcspi1_ick = {
        .prcm_mod       = CORE_MOD,
        .clkdm          = { .name = "core_l4_clkdm" },
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2031,7 +2021,7 @@ static struct clk mcspi1_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2043,7 +2033,7 @@ static struct clk mcspi2_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2055,7 +2045,7 @@ static struct clk mcspi2_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2067,7 +2057,7 @@ static struct clk mcspi3_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2079,7 +2069,7 @@ static struct clk mcspi3_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2090,7 +2080,7 @@ static struct clk uart1_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2101,7 +2091,7 @@ static struct clk uart1_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2112,7 +2102,7 @@ static struct clk uart2_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2123,7 +2113,7 @@ static struct clk uart2_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2134,7 +2124,7 @@ static struct clk uart3_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2145,7 +2135,7 @@ static struct clk uart3_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2156,7 +2146,7 @@ static struct clk gpios_ick = {
        .prcm_mod       = WKUP_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2167,7 +2157,7 @@ static struct clk gpios_fck = {
        .prcm_mod       = WKUP_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "prm_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2179,7 +2169,7 @@ static struct clk mpu_wdt_ick = {
        .prcm_mod       = WKUP_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "prm_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2191,7 +2181,7 @@ static struct clk mpu_wdt_fck = {
        .prcm_mod       = WKUP_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "prm_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2203,7 +2193,7 @@ static struct clk sync_32k_ick = {
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                ENABLE_ON_INIT,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2215,7 +2205,7 @@ static struct clk wdt1_ick = {
        .prcm_mod       = WKUP_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "prm_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2227,7 +2217,7 @@ static struct clk omapctrl_ick = {
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                ENABLE_ON_INIT,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2238,7 +2228,7 @@ static struct clk icr_ick = {
        .prcm_mod       = WKUP_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP2430_EN_ICR_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2249,7 +2239,7 @@ static struct clk cam_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2265,7 +2255,7 @@ static struct clk cam_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l3_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2276,7 +2266,7 @@ static struct clk mailboxes_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2287,7 +2277,7 @@ static struct clk wdt4_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2298,7 +2288,7 @@ static struct clk wdt4_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2309,7 +2299,7 @@ static struct clk wdt3_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2320,7 +2310,7 @@ static struct clk wdt3_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2331,7 +2321,7 @@ static struct clk mspro_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2342,7 +2332,7 @@ static struct clk mspro_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2353,7 +2343,7 @@ static struct clk mmc_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2364,7 +2354,7 @@ static struct clk mmc_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2375,7 +2365,7 @@ static struct clk fac_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2386,7 +2376,7 @@ static struct clk fac_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2397,7 +2387,7 @@ static struct clk eac_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2408,7 +2398,7 @@ static struct clk eac_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2419,7 +2409,7 @@ static struct clk hdq_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2430,7 +2420,7 @@ static struct clk hdq_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2442,7 +2432,7 @@ static struct clk i2c2_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2454,7 +2444,7 @@ static struct clk i2c2_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2466,7 +2456,7 @@ static struct clk i2chs2_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2478,7 +2468,7 @@ static struct clk i2c1_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2490,7 +2480,7 @@ static struct clk i2c1_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2502,7 +2492,7 @@ static struct clk i2chs1_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2538,7 +2528,7 @@ static struct clk vlynq_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l3_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2574,10 +2564,10 @@ static struct clk vlynq_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
        .clkdm          = { .name = "core_l3_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
        .clksel         = vlynq_fck_clksel,
        .recalc         = &omap2_clksel_recalc,
@@ -2591,7 +2581,7 @@ static struct clk sdrc_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN3),
+       .enable_reg     = CM_ICLKEN3,
        .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2602,7 +2592,7 @@ static struct clk des_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+       .enable_reg     = OMAP24XX_CM_ICLKEN4,
        .enable_bit     = OMAP24XX_EN_DES_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2613,7 +2603,7 @@ static struct clk sha_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+       .enable_reg     = OMAP24XX_CM_ICLKEN4,
        .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2624,7 +2614,7 @@ static struct clk rng_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+       .enable_reg     = OMAP24XX_CM_ICLKEN4,
        .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2635,7 +2625,7 @@ static struct clk aes_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+       .enable_reg     = OMAP24XX_CM_ICLKEN4,
        .enable_bit     = OMAP24XX_EN_AES_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2646,7 +2636,7 @@ static struct clk pka_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+       .enable_reg     = OMAP24XX_CM_ICLKEN4,
        .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2657,7 +2647,7 @@ static struct clk usb_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
        .clkdm          = { .name = "core_l3_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2668,7 +2658,7 @@ static struct clk usbhs_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l3_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2680,7 +2670,7 @@ static struct clk mmchs1_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2692,7 +2682,7 @@ static struct clk mmchs1_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l3_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2704,7 +2694,7 @@ static struct clk mmchs2_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2716,7 +2706,7 @@ static struct clk mmchs2_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2727,7 +2717,7 @@ static struct clk gpio5_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2738,7 +2728,7 @@ static struct clk gpio5_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2749,7 +2739,7 @@ static struct clk mdm_intc_ick = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2761,7 +2751,7 @@ static struct clk mmchsdb1_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
        .recalc         = &followparent_recalc,
 };
@@ -2773,7 +2763,7 @@ static struct clk mmchsdb2_fck = {
        .prcm_mod       = CORE_MOD,
        .flags          = CLOCK_IN_OMAP243X,
        .clkdm          = { .name = "core_l4_clkdm" },
-       .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_reg     = OMAP24XX_CM_FCLKEN2,
        .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
        .recalc         = &followparent_recalc,
 };

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 13baf2fe76ff0e88cde94c36cf081ab35241cae8..c89d6bcb197ca3069775b7704f233eaab2bb0c83 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -66,10 +66,10 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
 
        dd = clk->dpll_data;
 
-       v = __raw_readl(dd->control_reg);
+       v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
        v &= ~dd->enable_mask;
        v |= clken_bits << __ffs(dd->enable_mask);
-       __raw_writel(v, dd->control_reg);
+       cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);
 }
 
 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
@@ -83,7 +83,8 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
 
        state <<= __ffs(dd->idlest_mask);
 
-       while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
+       while (((cm_read_mod_reg(clk->prcm_mod, dd->idlest_reg)
+                & dd->idlest_mask) != state) &&
               i < MAX_DPLL_WAIT_TRIES) {
                i++;
                udelay(1);
@@ -356,17 +357,17 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
        _omap3_noncore_dpll_bypass(clk);
 
        /* Set jitter correction */
-       v = __raw_readl(dd->control_reg);
+       v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
        v &= ~dd->freqsel_mask;
        v |= freqsel << __ffs(dd->freqsel_mask);
-       __raw_writel(v, dd->control_reg);
+       cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);
 
        /* Set DPLL multiplier, divider */
-       v = __raw_readl(dd->mult_div1_reg);
+       v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
        v &= ~(dd->mult_mask | dd->div1_mask);
        v |= m << __ffs(dd->mult_mask);
        v |= (n - 1) << __ffs(dd->div1_mask);
-       __raw_writel(v, dd->mult_div1_reg);
+       cm_write_mod_reg(v, clk->prcm_mod, dd->mult_div1_reg);
 
        /* We let the clock framework set the other output dividers later */
 
@@ -524,7 +525,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
 
        dd = clk->dpll_data;
 
-       v = __raw_readl(dd->autoidle_reg);
+       v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
        v &= dd->autoidle_mask;
        v >>= __ffs(dd->autoidle_mask);
 
@@ -555,10 +556,10 @@ static void omap3_dpll_allow_idle(struct clk *clk)
         * by writing 0x5 instead of 0x1.  Add some mechanism to
         * optionally enter this mode.
         */
-       v = __raw_readl(dd->autoidle_reg);
+       v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
        v &= ~dd->autoidle_mask;
        v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
-       __raw_writel(v, dd->autoidle_reg);
+       cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg);
 }
 
 /**
@@ -577,10 +578,10 @@ static void omap3_dpll_deny_idle(struct clk *clk)
 
        dd = clk->dpll_data;
 
-       v = __raw_readl(dd->autoidle_reg);
+       v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
        v &= ~dd->autoidle_mask;
        v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
-       __raw_writel(v, dd->autoidle_reg);
+       cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg);
 }
 
 /* Clock control for DPLL outputs */
@@ -610,7 +611,7 @@ static void omap3_clkoutx2_recalc(struct clk *clk)
 
        WARN_ON(!dd->idlest_reg || !dd->idlest_mask);
 
-       v = __raw_readl(dd->idlest_reg) & dd->idlest_mask;
+       v = cm_read_mod_reg(pclk->prcm_mod, dd->idlest_reg) & dd->idlest_mask;
        if (!v)
                clk->rate = clk->parent->rate;
        else

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 9727e1df14c247a703e327820cf389aaaf949810..ccdd3f2476fa1cec27147d7cfea5ae9a0fdfe16b 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -58,18 +58,6 @@ static struct clk dpll2_fck;
 #define DPLL_LOW_POWER_BYPASS          0x5
 #define DPLL_LOCKED                    0x7
 
-#define _OMAP34XX_PRM_REGADDR(module, reg)                             \
-       ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
-
-#define OMAP3430_PRM_CLKSRC_CTRL                                       \
-       _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
-
-#define OMAP3430_PRM_CLKSEL                                            \
-       _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
-
-#define OMAP3430_PRM_CLKOUT_CTRL                                       \
-       _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
-
 /* PRM CLOCKS */
 
 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
@@ -192,7 +180,7 @@ static struct clk osc_sys_ck = {
        .name           = "osc_sys_ck",
        .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
+       .clksel_reg     = OMAP3_PRM_CLKSEL_OFFSET,
        .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
        .clksel         = osc_sys_clksel,
        /* REVISIT: deal with autoextclkmode? */
@@ -220,7 +208,7 @@ static struct clk sys_ck = {
        .parent         = &osc_sys_ck,
        .prcm_mod       = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
+       .clksel_reg     = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
        .clksel_mask    = OMAP_SYSCLKDIV_MASK,
        .clksel         = sys_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -253,7 +241,7 @@ static struct clk sys_clkout1 = {
        .name           = "sys_clkout1",
        .parent         = &osc_sys_ck,
        .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
-       .enable_reg     = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
+       .enable_reg     = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
        .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -284,29 +272,23 @@ static const struct clksel_rate div16_dpll_rates[] = {
        { .div = 0 }
 };
 
-#define _OMAP34XX_CM_REGADDR(module, reg)                              \
-       ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
-
-#define _OMAP34XX_PRM_REGADDR(module, reg)                             \
-       ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
-
 /* DPLL1 */
 /* MPU clock source */
 /* Type: DPLL */
 static struct dpll_data dpll1_dd = {
-       .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+       .mult_div1_reg  = OMAP3430_CM_CLKSEL1_PLL,
        .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
        .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
-       .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
+       .control_reg    = OMAP3430_CM_CLKEN_PLL,
        .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
        .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
        .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
        .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
-       .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+       .autoidle_reg   = OMAP3430_CM_AUTOIDLE_PLL,
        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
-       .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+       .idlest_reg     = OMAP3430_CM_IDLEST_PLL,
        .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
        .bypass_clk     = &dpll1_fck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -354,7 +336,7 @@ static struct clk dpll1_x2m2_ck = {
        .parent         = &dpll1_x2_ck,
        .prcm_mod       = MPU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
+       .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div16_dpll1_x2m2_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -368,20 +350,20 @@ static struct clk dpll1_x2m2_ck = {
 /* Type: DPLL */
 
 static struct dpll_data dpll2_dd = {
-       .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+       .mult_div1_reg  = OMAP3430_CM_CLKSEL1_PLL,
        .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
        .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
-       .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
+       .control_reg    = OMAP3430_CM_CLKEN_PLL,
        .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
                                (1 << DPLL_LOW_POWER_BYPASS),
        .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
        .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
        .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
-       .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+       .autoidle_reg   = OMAP3430_CM_AUTOIDLE_PLL,
        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
-       .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
+       .idlest_reg     = OMAP3430_CM_IDLEST_PLL,
        .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
        .bypass_clk     = &dpll2_fck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -417,8 +399,7 @@ static struct clk dpll2_m2_ck = {
        .parent         = &dpll2_ck,
        .prcm_mod       = OMAP3430_IVA2_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
-                                         OMAP3430_CM_CLKSEL2_PLL),
+       .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div16_dpll2_m2x2_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -433,18 +414,18 @@ static struct clk dpll2_m2_ck = {
  * REVISIT: Also supports fast relock bypass - not included below
  */
 static struct dpll_data dpll3_dd = {
-       .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .mult_div1_reg  = CM_CLKSEL1,
        .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
        .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
-       .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .control_reg    = CM_CLKEN,
        .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
        .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
        .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
-       .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+       .autoidle_reg   = CM_AUTOIDLE,
        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
-       .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
+       .idlest_reg     = CM_IDLEST,
        .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
        .bypass_clk     = &sys_ck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -522,7 +503,7 @@ static struct clk dpll3_m2_ck = {
        .parent         = &dpll3_ck,
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div31_dpll3m2_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -563,7 +544,7 @@ static struct clk dpll3_m3_ck = {
        .parent         = &dpll3_ck,
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
        .clksel         = div16_dpll3_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -577,7 +558,7 @@ static struct clk dpll3_m3x2_ck = {
        .name           = "dpll3_m3x2_ck",
        .parent         = &dpll3_m3_ck,
        .prcm_mod       = PLL_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
        .clkdm          = { .name = "dpll3_clkdm" },
@@ -597,19 +578,19 @@ static struct clk emu_core_alwon_ck = {
 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 /* Type: DPLL */
 static struct dpll_data dpll4_dd = {
-       .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+       .mult_div1_reg  = CM_CLKSEL2,
        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
        .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
-       .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .control_reg    = CM_CLKEN,
        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
-       .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+       .autoidle_reg   = CM_AUTOIDLE,
        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
-       .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
+       .idlest_reg     = CM_IDLEST,
        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
        .bypass_clk     = &sys_ck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -656,7 +637,7 @@ static struct clk dpll4_m2_ck = {
        .parent         = &dpll4_ck,
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
+       .clksel_reg     = OMAP3430_CM_CLKSEL3,
        .clksel_mask    = OMAP3430_DIV_96M_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -670,7 +651,7 @@ static struct clk dpll4_m2x2_ck = {
        .name           = "dpll4_m2x2_ck",
        .parent         = &dpll4_m2_ck,
        .prcm_mod       = PLL_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
@@ -722,7 +703,7 @@ static struct clk omap_96m_fck = {
        .parent         = &sys_ck,
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
        .clksel         = omap_96m_fck_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -737,7 +718,7 @@ static struct clk dpll4_m3_ck = {
        .parent         = &dpll4_ck,
        .prcm_mod       = OMAP3430_DSS_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -752,7 +733,7 @@ static struct clk dpll4_m3x2_ck = {
        .parent         = &dpll4_m3_ck,
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
@@ -779,7 +760,7 @@ static struct clk omap_54m_fck = {
        .name           = "omap_54m_fck",
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
        .clksel         = omap_54m_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -808,7 +789,7 @@ static struct clk omap_48m_fck = {
        .name           = "omap_48m_fck",
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
        .clksel         = omap_48m_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -833,7 +814,7 @@ static struct clk dpll4_m4_ck = {
        .parent         = &dpll4_ck,
        .prcm_mod       = OMAP3430_DSS_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -847,7 +828,7 @@ static struct clk dpll4_m4x2_ck = {
        .name           = "dpll4_m4x2_ck",
        .parent         = &dpll4_m4_ck,
        .prcm_mod       = PLL_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
@@ -860,7 +841,7 @@ static struct clk dpll4_m5_ck = {
        .parent         = &dpll4_ck,
        .prcm_mod       = OMAP3430_CAM_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -874,7 +855,7 @@ static struct clk dpll4_m5x2_ck = {
        .name           = "dpll4_m5x2_ck",
        .parent         = &dpll4_m5_ck,
        .prcm_mod       = PLL_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
@@ -887,7 +868,7 @@ static struct clk dpll4_m6_ck = {
        .parent         = &dpll4_ck,
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -902,7 +883,7 @@ static struct clk dpll4_m6x2_ck = {
        .parent         = &dpll4_m6_ck,
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
@@ -923,19 +904,19 @@ static struct clk emu_per_alwon_ck = {
 /* Type: DPLL */
 /* 3430ES2 only */
 static struct dpll_data dpll5_dd = {
-       .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
+       .mult_div1_reg  = OMAP3430ES2_CM_CLKSEL4,
        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
        .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
-       .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
+       .control_reg    = OMAP3430ES2_CM_CLKEN2,
        .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
        .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
        .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
        .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
-       .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
+       .autoidle_reg   = OMAP3430ES2_CM_AUTOIDLE2_PLL,
        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
-       .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+       .idlest_reg     = CM_IDLEST2,
        .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
        .bypass_clk     = &sys_ck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -967,7 +948,7 @@ static struct clk dpll5_m2_ck = {
        .parent         = &dpll5_ck,
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
+       .clksel_reg     = OMAP3430ES2_CM_CLKSEL5,
        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
        .clksel         = div16_dpll5_clksel,
        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
@@ -1010,9 +991,9 @@ static struct clk clkout2_src_ck = {
        .name           = "clkout2_src_ck",
        .prcm_mod       = OMAP3430_CCR_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
+       .enable_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
        .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
-       .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
+       .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
        .clksel         = clkout2_src_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
@@ -1038,7 +1019,7 @@ static struct clk sys_clkout2 = {
        .name           = "sys_clkout2",
        .prcm_mod       = OMAP3430_CCR_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
+       .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
        .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
        .clksel         = sys_clkout2_clksel,
        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
@@ -1076,7 +1057,7 @@ static struct clk dpll1_fck = {
        .parent         = &core_ck,
        .prcm_mod       = MPU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+       .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
        .clksel         = div4_core_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1111,7 +1092,7 @@ static struct clk arm_fck = {
        .parent         = &mpu_ck,
        .prcm_mod       = MPU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+       .clksel_reg     = OMAP3430_CM_IDLEST_PLL,
        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
        .clksel         = arm_fck_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1140,7 +1121,7 @@ static struct clk dpll2_fck = {
        .parent         = &core_ck,
        .prcm_mod       = OMAP3430_IVA2_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+       .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
        .clksel         = div4_core_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1154,7 +1135,7 @@ static struct clk iva2_ck = {
        .parent         = &dpll2_m2_ck,
        .prcm_mod       = OMAP3430_IVA2_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
        .clkdm          = { .name = "iva2_clkdm" },
@@ -1173,7 +1154,7 @@ static struct clk l3_ick = {
        .parent         = &core_ck,
        .prcm_mod       = CORE_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
        .clksel         = div2_core_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1192,7 +1173,7 @@ static struct clk l4_ick = {
        .parent         = &l3_ick,
        .prcm_mod       = CORE_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
        .clksel         = div2_l3_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1212,7 +1193,7 @@ static struct clk rm_ick = {
        .parent         = &l4_ick,
        .prcm_mod       = WKUP_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
        .clksel         = div2_l4_clksel,
        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
@@ -1235,7 +1216,7 @@ static struct clk gfx_l3_ck = {
        .parent         = &l3_ick,
        .prcm_mod       = GFX_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP_EN_GFX_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "gfx_3430es1_clkdm" },
@@ -1247,7 +1228,7 @@ static struct clk gfx_l3_fck = {
        .parent         = &gfx_l3_ck,
        .prcm_mod       = GFX_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
        .clksel         = gfx_l3_clksel,
        .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
@@ -1268,7 +1249,7 @@ static struct clk gfx_cg1_ck = {
        .name           = "gfx_cg1_ck",
        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
        .prcm_mod       = GFX_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "gfx_3430es1_clkdm" },
@@ -1279,7 +1260,7 @@ static struct clk gfx_cg2_ck = {
        .name           = "gfx_cg2_ck",
        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
        .prcm_mod       = GFX_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "gfx_3430es1_clkdm" },
@@ -1310,9 +1291,9 @@ static struct clk sgx_fck = {
        .name           = "sgx_fck",
        .init           = &omap2_init_clksel_parent,
        .prcm_mod       = OMAP3430ES2_SGX_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
        .clksel         = sgx_clksel,
        .flags          = CLOCK_IN_OMAP3430ES2,
@@ -1324,7 +1305,7 @@ static struct clk sgx_ick = {
        .name           = "sgx_ick",
        .parent         = &l3_ick,
        .prcm_mod       = OMAP3430ES2_SGX_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "sgx_clkdm" },
@@ -1337,7 +1318,7 @@ static struct clk d2d_26m_fck = {
        .name           = "d2d_26m_fck",
        .parent         = &sys_ck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "d2d_clkdm" },
@@ -1355,9 +1336,9 @@ static struct clk gpt10_fck = {
        .parent         = &sys_ck,
        .prcm_mod       = CORE_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -1370,9 +1351,9 @@ static struct clk gpt11_fck = {
        .parent         = &sys_ck,
        .prcm_mod       = CORE_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -1384,7 +1365,7 @@ static struct clk cpefuse_fck = {
        .name           = "cpefuse_fck",
        .parent         = &sys_ck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+       .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
        .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "cm_clkdm" },
@@ -1395,7 +1376,7 @@ static struct clk ts_fck = {
        .name           = "ts_fck",
        .parent         = &omap_32k_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+       .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
        .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1406,7 +1387,7 @@ static struct clk usbtll_fck = {
        .name           = "usbtll_fck",
        .parent         = &dpll5_m2_ck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+       .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1429,7 +1410,7 @@ static struct clk mmchs3_fck = {
        .id             = 3,
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1441,7 +1422,7 @@ static struct clk mmchs2_fck = {
        .id             = 2,
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1452,7 +1433,7 @@ static struct clk mspro_fck = {
        .name           = "mspro_fck",
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1464,7 +1445,7 @@ static struct clk mmchs1_fck = {
        .id             = 1,
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1476,7 +1457,7 @@ static struct clk i2c3_fck = {
        .id             = 3,
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1488,7 +1469,7 @@ static struct clk i2c2_fck = {
        .id             = 2,
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1500,7 +1481,7 @@ static struct clk i2c1_fck = {
        .id             = 1,
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1532,7 +1513,7 @@ static struct clk mcbsp5_src_fck = {
        .id             = 5,
        .prcm_mod       = CLK_REG_IN_SCM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+       .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
        .clksel         = mcbsp_15_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -1545,7 +1526,7 @@ static struct clk mcbsp5_fck = {
        .id             = 5,
        .parent         = &mcbsp5_src_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1557,7 +1538,7 @@ static struct clk mcbsp1_src_fck = {
        .id             = 1,
        .prcm_mod       = CLK_REG_IN_SCM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+       .clksel_reg     = OMAP2_CONTROL_DEVCONF0,
        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
        .clksel         = mcbsp_15_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -1570,7 +1551,7 @@ static struct clk mcbsp1_fck = {
        .id             = 1,
        .parent         = &mcbsp1_src_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1593,7 +1574,7 @@ static struct clk mcspi4_fck = {
        .id             = 4,
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1605,7 +1586,7 @@ static struct clk mcspi3_fck = {
        .id             = 3,
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1617,7 +1598,7 @@ static struct clk mcspi2_fck = {
        .id             = 2,
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1629,7 +1610,7 @@ static struct clk mcspi1_fck = {
        .id             = 1,
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1640,7 +1621,7 @@ static struct clk uart2_fck = {
        .name           = "uart2_fck",
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1651,7 +1632,7 @@ static struct clk uart1_fck = {
        .name           = "uart1_fck",
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1662,7 +1643,7 @@ static struct clk fshostusb_fck = {
        .name           = "fshostusb_fck",
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1684,7 +1665,7 @@ static struct clk hdq_fck = {
        .name           = "hdq_fck",
        .parent         = &core_12m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1712,9 +1693,9 @@ static struct clk ssi_ssr_fck = {
        .name           = "ssi_ssr_fck",
        .init           = &omap2_init_clksel_parent,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
        .clksel         = ssi_ssr_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
@@ -1752,7 +1733,7 @@ static struct clk hsotgusb_ick = {
        .name           = "hsotgusb_ick",
        .parent         = &core_l3_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l3_clkdm" },
@@ -1763,7 +1744,7 @@ static struct clk sdrc_ick = {
        .name           = "sdrc_ick",
        .parent         = &core_l3_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
        .clkdm          = { .name = "core_l3_clkdm" },
@@ -1794,7 +1775,7 @@ static struct clk pka_ick = {
        .name           = "pka_ick",
        .parent         = &security_l3_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP3430_EN_PKA_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l3_clkdm" },
@@ -1816,7 +1797,7 @@ static struct clk usbtll_ick = {
        .name           = "usbtll_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+       .enable_reg     = CM_ICLKEN3,
        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1828,7 +1809,7 @@ static struct clk mmchs3_ick = {
        .id             = 3,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1840,7 +1821,7 @@ static struct clk icr_ick = {
        .name           = "icr_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_ICR_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1851,7 +1832,7 @@ static struct clk aes2_ick = {
        .name           = "aes2_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_AES2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1862,7 +1843,7 @@ static struct clk sha12_ick = {
        .name           = "sha12_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1873,7 +1854,7 @@ static struct clk des2_ick = {
        .name           = "des2_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_DES2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1885,7 +1866,7 @@ static struct clk mmchs2_ick = {
        .id             = 2,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1897,7 +1878,7 @@ static struct clk mmchs1_ick = {
        .id             = 1,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1908,7 +1889,7 @@ static struct clk mspro_ick = {
        .name           = "mspro_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1919,7 +1900,7 @@ static struct clk hdq_ick = {
        .name           = "hdq_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1931,7 +1912,7 @@ static struct clk mcspi4_ick = {
        .id             = 4,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1943,7 +1924,7 @@ static struct clk mcspi3_ick = {
        .id             = 3,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1955,7 +1936,7 @@ static struct clk mcspi2_ick = {
        .id             = 2,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1967,7 +1948,7 @@ static struct clk mcspi1_ick = {
        .id             = 1,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1979,7 +1960,7 @@ static struct clk i2c3_ick = {
        .id             = 3,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1991,7 +1972,7 @@ static struct clk i2c2_ick = {
        .id             = 2,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2003,7 +1984,7 @@ static struct clk i2c1_ick = {
        .id             = 1,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2014,7 +1995,7 @@ static struct clk uart2_ick = {
        .name           = "uart2_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2025,7 +2006,7 @@ static struct clk uart1_ick = {
        .name           = "uart1_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2036,7 +2017,7 @@ static struct clk gpt11_ick = {
        .name           = "gpt11_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2047,7 +2028,7 @@ static struct clk gpt10_ick = {
        .name           = "gpt10_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2059,7 +2040,7 @@ static struct clk mcbsp5_ick = {
        .id             = 5,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2071,7 +2052,7 @@ static struct clk mcbsp1_ick = {
        .id             = 1,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2082,7 +2063,7 @@ static struct clk fac_ick = {
        .name           = "fac_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2093,7 +2074,7 @@ static struct clk mailboxes_ick = {
        .name           = "mailboxes_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2104,7 +2085,7 @@ static struct clk omapctrl_ick = {
        .name           = "omapctrl_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2126,7 +2107,7 @@ static struct clk ssi_ick = {
        .name           = "ssi_ick",
        .parent         = &ssi_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2146,9 +2127,9 @@ static struct clk usb_l4_ick = {
        .parent         = &l4_ick,
        .prcm_mod       = CORE_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
        .clksel         = usb_l4_clksel,
        .flags          = CLOCK_IN_OMAP3430ES1,
@@ -2173,7 +2154,7 @@ static struct clk aes1_ick = {
        .name           = "aes1_ick",
        .parent         = &security_l4_ick2,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP3430_EN_AES1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2184,7 +2165,7 @@ static struct clk rng_ick = {
        .name           = "rng_ick",
        .parent         = &security_l4_ick2,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP3430_EN_RNG_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2195,7 +2176,7 @@ static struct clk sha11_ick = {
        .name           = "sha11_ick",
        .parent         = &security_l4_ick2,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2206,7 +2187,7 @@ static struct clk des1_ick = {
        .name           = "des1_ick",
        .parent         = &security_l4_ick2,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP3430_EN_DES1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2218,7 +2199,7 @@ static struct clk dss1_alwon_fck = {
        .name           = "dss1_alwon_fck",
        .parent         = &dpll4_m4x2_ck,
        .prcm_mod       = OMAP3430_DSS_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "dss_clkdm" },
@@ -2229,7 +2210,7 @@ static struct clk dss_tv_fck = {
        .name           = "dss_tv_fck",
        .parent         = &omap_54m_fck,
        .prcm_mod       = OMAP3430_DSS_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_TV_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
@@ -2240,7 +2221,7 @@ static struct clk dss_96m_fck = {
        .name           = "dss_96m_fck",
        .parent         = &omap_96m_fck,
        .prcm_mod       = OMAP3430_DSS_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_TV_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "dss_clkdm" },
@@ -2251,7 +2232,7 @@ static struct clk dss2_alwon_fck = {
        .name           = "dss2_alwon_fck",
        .parent         = &sys_ck,
        .prcm_mod       = OMAP3430_DSS_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "dss_clkdm" },
@@ -2263,7 +2244,7 @@ static struct clk dss_ick = {
        .name           = "dss_ick",
        .parent         = &l4_ick,
        .prcm_mod       = OMAP3430_DSS_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "dss_clkdm" },
@@ -2276,7 +2257,7 @@ static struct clk cam_mclk = {
        .name           = "cam_mclk",
        .parent         = &dpll4_m5x2_ck,
        .prcm_mod       = OMAP3430_CAM_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "cam_clkdm" },
@@ -2288,7 +2269,7 @@ static struct clk cam_ick = {
        .name           = "cam_ick",
        .parent         = &l4_ick,
        .prcm_mod       = OMAP3430_CAM_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "cam_clkdm" },
@@ -2299,7 +2280,7 @@ static struct clk csi2_96m_fck = {
        .name           = "csi2_96m_fck",
        .parent         = &core_96m_fck,
        .prcm_mod       = OMAP3430_CAM_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "cam_clkdm" },
@@ -2312,7 +2293,7 @@ static struct clk usbhost_120m_fck = {
        .name           = "usbhost_120m_fck",
        .parent         = &dpll5_m2_ck,
        .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "usbhost_clkdm" },
@@ -2323,7 +2304,7 @@ static struct clk usbhost_48m_fck = {
        .name           = "usbhost_48m_fck",
        .parent         = &omap_48m_fck,
        .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "usbhost_clkdm" },
@@ -2335,7 +2316,7 @@ static struct clk usbhost_ick = {
        .name           = "usbhost_ick",
        .parent         = &l4_ick,
        .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "usbhost_clkdm" },
@@ -2372,9 +2353,9 @@ static struct clk usim_fck = {
        .name           = "usim_fck",
        .prcm_mod       = WKUP_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
        .clksel         = usim_clksel,
        .flags          = CLOCK_IN_OMAP3430ES2,
@@ -2387,9 +2368,9 @@ static struct clk gpt1_fck = {
        .name           = "gpt1_fck",
        .prcm_mod       = WKUP_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2409,7 +2390,7 @@ static struct clk gpio1_fck = {
        .name           = "gpio1_fck",
        .parent         = &wkup_32k_fck,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2420,7 +2401,7 @@ static struct clk wdt2_fck = {
        .name           = "wdt2_fck",
        .parent         = &wkup_32k_fck,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2441,7 +2422,7 @@ static struct clk usim_ick = {
        .name           = "usim_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2452,7 +2433,7 @@ static struct clk wdt2_ick = {
        .name           = "wdt2_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2463,7 +2444,7 @@ static struct clk wdt1_ick = {
        .name           = "wdt1_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2474,7 +2455,7 @@ static struct clk gpio1_ick = {
        .name           = "gpio1_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2485,7 +2466,7 @@ static struct clk omap_32ksync_ick = {
        .name           = "omap_32ksync_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2496,7 +2477,7 @@ static struct clk gpt12_ick = {
        .name           = "gpt12_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2507,7 +2488,7 @@ static struct clk gpt1_ick = {
        .name           = "gpt1_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2540,7 +2521,7 @@ static struct clk uart3_fck = {
        .name           = "uart3_fck",
        .parent         = &per_48m_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2551,9 +2532,9 @@ static struct clk gpt2_fck = {
        .name           = "gpt2_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2565,9 +2546,9 @@ static struct clk gpt3_fck = {
        .name           = "gpt3_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2579,9 +2560,9 @@ static struct clk gpt4_fck = {
        .name           = "gpt4_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2593,9 +2574,9 @@ static struct clk gpt5_fck = {
        .name           = "gpt5_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2607,9 +2588,9 @@ static struct clk gpt6_fck = {
        .name           = "gpt6_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2621,9 +2602,9 @@ static struct clk gpt7_fck = {
        .name           = "gpt7_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2635,9 +2616,9 @@ static struct clk gpt8_fck = {
        .name           = "gpt8_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2649,9 +2630,9 @@ static struct clk gpt9_fck = {
        .name           = "gpt9_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2671,7 +2652,7 @@ static struct clk gpio6_fck = {
        .name           = "gpio6_fck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2682,7 +2663,7 @@ static struct clk gpio5_fck = {
        .name           = "gpio5_fck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2693,7 +2674,7 @@ static struct clk gpio4_fck = {
        .name           = "gpio4_fck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2704,7 +2685,7 @@ static struct clk gpio3_fck = {
        .name           = "gpio3_fck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2715,7 +2696,7 @@ static struct clk gpio2_fck = {
        .name           = "gpio2_fck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2726,7 +2707,7 @@ static struct clk wdt3_fck = {
        .name           = "wdt3_fck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2746,7 +2727,7 @@ static struct clk gpio6_ick = {
        .name           = "gpio6_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2757,7 +2738,7 @@ static struct clk gpio5_ick = {
        .name           = "gpio5_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2768,7 +2749,7 @@ static struct clk gpio4_ick = {
        .name           = "gpio4_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2779,7 +2760,7 @@ static struct clk gpio3_ick = {
        .name           = "gpio3_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2790,7 +2771,7 @@ static struct clk gpio2_ick = {
        .name           = "gpio2_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2801,7 +2782,7 @@ static struct clk wdt3_ick = {
        .name           = "wdt3_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2812,7 +2793,7 @@ static struct clk uart3_ick = {
        .name           = "uart3_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2823,7 +2804,7 @@ static struct clk gpt9_ick = {
        .name           = "gpt9_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2834,7 +2815,7 @@ static struct clk gpt8_ick = {
        .name           = "gpt8_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2845,7 +2826,7 @@ static struct clk gpt7_ick = {
        .name           = "gpt7_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2856,7 +2837,7 @@ static struct clk gpt6_ick = {
        .name           = "gpt6_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2867,7 +2848,7 @@ static struct clk gpt5_ick = {
        .name           = "gpt5_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2878,7 +2859,7 @@ static struct clk gpt4_ick = {
        .name           = "gpt4_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2889,7 +2870,7 @@ static struct clk gpt3_ick = {
        .name           = "gpt3_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2900,7 +2881,7 @@ static struct clk gpt2_ick = {
        .name           = "gpt2_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2912,7 +2893,7 @@ static struct clk mcbsp2_ick = {
        .id             = 2,
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2924,7 +2905,7 @@ static struct clk mcbsp3_ick = {
        .id             = 3,
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2936,7 +2917,7 @@ static struct clk mcbsp4_ick = {
        .id             = 4,
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2954,7 +2935,7 @@ static struct clk mcbsp2_src_fck = {
        .id             = 2,
        .prcm_mod       = CLK_REG_IN_SCM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+       .clksel_reg     = OMAP2_CONTROL_DEVCONF0,
        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
        .clksel         = mcbsp_234_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2967,7 +2948,7 @@ static struct clk mcbsp2_fck = {
        .id             = 2,
        .parent         = &mcbsp2_src_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2979,7 +2960,7 @@ static struct clk mcbsp3_src_fck = {
        .id             = 3,
        .prcm_mod       = CLK_REG_IN_SCM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+       .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
        .clksel         = mcbsp_234_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2992,7 +2973,7 @@ static struct clk mcbsp3_fck = {
        .id             = 3,
        .parent         = &mcbsp3_src_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -3004,7 +2985,7 @@ static struct clk mcbsp4_src_fck = {
        .id             = 4,
        .prcm_mod       = CLK_REG_IN_SCM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+       .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
        .clksel         = mcbsp_234_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -3017,7 +2998,7 @@ static struct clk mcbsp4_fck = {
        .id             = 4,
        .parent         = &mcbsp4_src_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -3065,7 +3046,7 @@ static struct clk emu_src_ck = {
        .name           = "emu_src_ck",
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
        .clksel         = emu_src_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3090,7 +3071,7 @@ static struct clk pclk_fck = {
        .name           = "pclk_fck",
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
        .clksel         = pclk_emu_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3114,7 +3095,7 @@ static struct clk pclkx2_fck = {
        .name           = "pclkx2_fck",
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
        .clksel         = pclkx2_emu_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3131,7 +3112,7 @@ static struct clk atclk_fck = {
        .name           = "atclk_fck",
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
        .clksel         = atclk_emu_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3143,7 +3124,7 @@ static struct clk traceclk_src_fck = {
        .name           = "traceclk_src_fck",
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
        .clksel         = emu_src_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3167,7 +3148,7 @@ static struct clk traceclk_fck = {
        .name           = "traceclk_fck",
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
        .clksel         = traceclk_clksel,
        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
@@ -3182,7 +3163,7 @@ static struct clk sr1_fck = {
        .name           = "sr1_fck",
        .parent         = &sys_ck,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_SR1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
        .clkdm          = { .name = "prm_clkdm" },
@@ -3194,7 +3175,7 @@ static struct clk sr2_fck = {
        .name           = "sr2_fck",
        .parent         = &sys_ck,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_SR2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
        .clkdm          = { .name = "prm_clkdm" },

diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index bacadcb0851cab1f14bf2098285fec171faf24c8..7750becd5d37c692295c29feb2037726460e003f 100644 (file)
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -33,8 +33,7 @@
 #define OMAP3430_CM_SYSCONFIG          OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
 #define OMAP3430_CM_POLCTRL            OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
 
-#define OMAP3430_CM_CLKOUT_CTRL                                                \
-                               OMAP34XX_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+#define OMAP3430_CM_CLKOUT_CTRL_OFFSET                 0x0070
 
 /*
  * Module specific CM registers from CM_BASE + domain offset

diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 7913248824adea312e176e2d7b0b380a34303a4c..f498a23ba0640ec36e56f11690a2580a51b18e28 100644 (file)
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -272,7 +272,6 @@ static void __init __omap2_set_globals(void)
        omap2_set_globals_sdrc(omap2_globals);
        omap2_set_globals_control(omap2_globals);
        omap2_set_globals_prcm(omap2_globals);
-       omap2_set_globals_clock24xx(omap2_globals);
 }
 
 #endif

diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index c428cdf5d65b1e9f3c2f43af1c4343f819158f92..f094d5b77779e34d91248bc917d3b05f7e3bd369 100644 (file)
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -31,7 +31,7 @@ struct clksel {
 };
 
 struct dpll_data {
-       void __iomem            *mult_div1_reg;
+       u16                     mult_div1_reg;
        u32                     mult_mask;
        u32                     div1_mask;
        u16                     last_rounded_m;
@@ -41,18 +41,18 @@ struct dpll_data {
        u16                     max_multiplier;
        u8                      max_divider;
        u32                     max_tolerance;
-       void __iomem            *idlest_reg;
+       u16                     idlest_reg;
        u32                     idlest_mask;
        struct clk              *bypass_clk;
 #  if defined(CONFIG_ARCH_OMAP3)
        u32                     freqsel_mask;
        u8                      modes;
-       void __iomem            *control_reg;
+       u16                     control_reg;
        u32                     enable_mask;
        u8                      auto_recal_bit;
        u8                      recal_en_bit;
        u8                      recal_st_bit;
-       void __iomem            *autoidle_reg;
+       u16                     autoidle_reg;
        u32                     autoidle_mask;
 #  endif
 };
@@ -67,7 +67,7 @@ struct clk {
        struct clk              *parent;
        unsigned long           rate;
        __u32                   flags;
-       void __iomem            *enable_reg;
+       u16                     enable_reg;
        __u8                    enable_bit;
        __s8                    usecount;
        void                    (*recalc)(struct clk *);
@@ -78,7 +78,7 @@ struct clk {
        void                    (*disable)(struct clk *);
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
        u8                      fixed_div;
-       void __iomem            *clksel_reg;
+       u16                     clksel_reg;
        u32                     clksel_mask;
        const struct clksel     *clksel;
        struct dpll_data        *dpll_data;
@@ -142,9 +142,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 #define DELAYED_APP            (1 << 9)        /* Delay application of clock */
 #define CONFIG_PARTICIPANT     (1 << 10)       /* Fundamental clock */
 #define ENABLE_ON_INIT         (1 << 11)       /* Enable upon framework init */
-#define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
-#define OFFSET_GR_MOD          (1 << 13)       /* 24xx GR_MOD reg as offset */
-/* bits 14-20 are currently free */
+#define INVERT_ENABLE          (1 << 12)       /* 0 enables, 1 disables */
+/* bits 13-20 are currently free */
 #define CLOCK_IN_OMAP310       (1 << 21)
 #define CLOCK_IN_OMAP730       (1 << 22)
 #define CLOCK_IN_OMAP1510      (1 << 23)