MN10300: Fix misaligned index-register addressing handling

Fix misalignment handling for an address calculated from the sum of two
registers.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c
index 61e65ec47db83ec739c8ec69d2ca9b9b3a6376d9..a59836804bc6f480cb053f9b5f41b91d562867b9 100644 (file)
--- a/arch/mn10300/mm/misalignment.c
+++ b/arch/mn10300/mm/misalignment.c
@@ -570,11 +570,11 @@ static int misalignment_addr(unsigned long *registers, unsigned params,
                        address += *postinc;
                        break;
                case DM1:
-                       postinc = &registers[Dreg_index[opcode >> 2 & 0x0c]];
+                       postinc = &registers[Dreg_index[opcode >> 2 & 0x03]];
                        address += *postinc;
                        break;
                case DM2:
-                       postinc = &registers[Dreg_index[opcode >> 4 & 0x30]];
+                       postinc = &registers[Dreg_index[opcode >> 4 & 0x03]];
                        address += *postinc;
                        break;
                case AM0:
@@ -582,11 +582,11 @@ static int misalignment_addr(unsigned long *registers, unsigned params,
                        address += *postinc;
                        break;
                case AM1:
-                       postinc = &registers[Areg_index[opcode >> 2 & 0x0c]];
+                       postinc = &registers[Areg_index[opcode >> 2 & 0x03]];
                        address += *postinc;
                        break;
                case AM2:
-                       postinc = &registers[Areg_index[opcode >> 4 & 0x30]];
+                       postinc = &registers[Areg_index[opcode >> 4 & 0x03]];
                        address += *postinc;
                        break;
                case RM0: