[MIPS] MT: Initialise all writable bits in Cause register to zero.

Recent 34Ks come out of reset with WP enabled on VPE 1 so we take an
immediate exception when starting the second VPE.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 93429a4d301296d2b550ce34d8f254ea93aaa8aa..766253c44f3fd8d3dcae954755702e13bb78506a 100644 (file)
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -203,7 +203,7 @@ void plat_smp_setup(void)
                                write_vpe_c0_config( read_c0_config());
 
                                /* make sure there are no software interrupts pending */
-                               write_vpe_c0_cause(read_vpe_c0_cause() & ~(C_SW1|C_SW0));
+                               write_vpe_c0_cause(0);
 
                                /* Propagate Config7 */
                                write_vpe_c0_config7(read_c0_config7());