x86: PAT Update validate_pat_support for intel CPUs

Pentium III and Core Solo/Duo CPUs have an erratum
" Page with PAT set to WC while associated MTRR is UC may consolidate to UC "
which can result in WC setting in PAT to be ineffective. We will disable
PAT on such CPUs, so that we can continue to use MTRR WC setting.

Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/addon_cpuid_features.c
index 84a8220a6072c0425b9da95fbb28b5a309cbfda1..a6ef672adbbae01e8da2abb5bf2ae1cb32c091be 100644 (file)
--- a/arch/x86/kernel/cpu/addon_cpuid_features.c
+++ b/arch/x86/kernel/cpu/addon_cpuid_features.c
@@ -56,9 +56,22 @@ void __cpuinit validate_pat_support(struct cpuinfo_x86 *c)
 
        switch (c->x86_vendor) {
        case X86_VENDOR_INTEL:
-               if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
+               /*
+                * There is a known erratum on Pentium III and Core Solo
+                * and Core Duo CPUs.
+                * " Page with PAT set to WC while associated MTRR is UC
+                *   may consolidate to UC "
+                * Because of this erratum, it is better to stick with
+                * setting WC in MTRR rather than using PAT on these CPUs.
+                *
+                * Enable PAT WC only on P4, Core 2 or later CPUs.
+                */
+               if (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 15))
                        return;
-               break;
+
+               pat_disable("PAT WC disabled due to known CPU erratum.");
+               return;
+
        case X86_VENDOR_AMD:
        case X86_VENDOR_CENTAUR:
        case X86_VENDOR_TRANSMETA: