]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[ARM] 5092/1: Fix the I-cache invalidation on ARMv6 and later CPUs
authorCatalin Marinas <catalin.marinas@arm.com>
Fri, 13 Jun 2008 09:28:36 +0000 (10:28 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Thu, 3 Jul 2008 15:39:57 +0000 (16:39 +0100)
This patch adds the I-cache invalidation in update_mmu_cache if the
corresponding vma is marked as executable. It also invalidates the
I-cache if a thread migrates to a CPU it never ran on.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mm/fault-armv.c
arch/arm/mm/flush.c
include/asm-arm/cacheflush.h
include/asm-arm/mmu_context.h

index 44558d5f9313c0e22d476bc07cd995c466666e66..fbfa26058442ccf5fb8dc0225b306f404eea2b6e 100644 (file)
@@ -144,13 +144,17 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
        page = pfn_to_page(pfn);
        mapping = page_mapping(page);
        if (mapping) {
+#ifndef CONFIG_SMP
                int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
 
                if (dirty)
                        __flush_dcache_page(mapping, page);
+#endif
 
                if (cache_is_vivt())
                        make_coherent(mapping, vma, addr, pfn);
+               else if (vma->vm_flags & VM_EXEC)
+                       __flush_icache_all();
        }
 }
 
index 9df507d36e0b9b0f0291395da5cecd007b627f0f..029ee65fda2b29ce832481fcadd36c83b475d344 100644 (file)
@@ -199,6 +199,8 @@ void flush_dcache_page(struct page *page)
                __flush_dcache_page(mapping, page);
                if (mapping && cache_is_vivt())
                        __flush_dcache_aliases(mapping, page);
+               else if (mapping)
+                       __flush_icache_all();
        }
 }
 EXPORT_SYMBOL(flush_dcache_page);
index 759a97b56eed8a189f1669f2d3ce9eb7fffba7e3..559fb4af1f626dd58452604e1e05230c5f2c2536 100644 (file)
@@ -410,6 +410,13 @@ extern void flush_dcache_page(struct page *);
 
 extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
 
+static inline void __flush_icache_all(void)
+{
+       asm("mcr        p15, 0, %0, c7, c5, 0   @ invalidate I-cache\n"
+           :
+           : "r" (0));
+}
+
 #define ARCH_HAS_FLUSH_ANON_PAGE
 static inline void flush_anon_page(struct vm_area_struct *vma,
                         struct page *page, unsigned long vmaddr)
index 6913d02ca5d61538e6b6a0be9f036993533c3424..91b9dfdfed526235131bc4b026039064be28f9d7 100644 (file)
@@ -97,6 +97,11 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #ifdef CONFIG_MMU
        unsigned int cpu = smp_processor_id();
 
+#ifdef CONFIG_SMP
+       /* check for possible thread migration */
+       if (!cpus_empty(next->cpu_vm_mask) && !cpu_isset(cpu, next->cpu_vm_mask))
+               __flush_icache_all();
+#endif
        if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) {
                check_context(next);
                cpu_switch_mm(next->pgd, next);