void __iomem            *ecc;
 };
 
+/*
+ * Enable NAND.
+ */
+static void at91_nand_enable(struct at91_nand_host *host)
+{
+       if (host->board->enable_pin)
+               at91_set_gpio_value(host->board->enable_pin, 0);
+}
+
+/*
+ * Disable NAND.
+ */
+static void at91_nand_disable(struct at91_nand_host *host)
+{
+       if (host->board->enable_pin)
+               at91_set_gpio_value(host->board->enable_pin, 1);
+}
+
 /*
  * Hardware specific access to control-lines
  */
        struct nand_chip *nand_chip = mtd->priv;
        struct at91_nand_host *host = nand_chip->priv;
 
-       if (host->board->enable_pin && (ctrl & NAND_CTRL_CHANGE)) {
+       if (ctrl & NAND_CTRL_CHANGE) {
                if (ctrl & NAND_NCE)
-                       at91_set_gpio_value(host->board->enable_pin, 0);
+                       at91_nand_enable(host);
                else
-                       at91_set_gpio_value(host->board->enable_pin, 1);
+                       at91_nand_disable(host);
        }
        if (cmd == NAND_CMD_NONE)
                return;
        return at91_get_gpio_value(host->board->rdy_pin);
 }
 
-/*
- * Enable NAND.
- */
-static void at91_nand_enable(struct at91_nand_host *host)
-{
-       if (host->board->enable_pin)
-               at91_set_gpio_value(host->board->enable_pin, 0);
-}
-
-/*
- * Disable NAND.
- */
-static void at91_nand_disable(struct at91_nand_host *host)
-{
-       if (host->board->enable_pin)
-               at91_set_gpio_value(host->board->enable_pin, 1);
-}
-
 /*
  * write oob for small pages
  */