]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[POWERPC] 4xx: Move 440EP(x) FPU setup from head_44x to cpu_setup_4xx
authorValentine Barshak <vbarshak@ru.mvista.com>
Fri, 21 Sep 2007 14:46:57 +0000 (00:46 +1000)
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>
Wed, 3 Oct 2007 12:20:17 +0000 (07:20 -0500)
The PowerPC 440EP(x) FPU init is currently done in head_44x
under ifdefs. Since we should support more then one board
in the same kernel, we move FPU initialization code from head_44x
to cpu_setup_44x and add cpu_setup callbacks for 440EP(x).

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
arch/powerpc/kernel/cpu_setup_44x.S
arch/powerpc/kernel/cputable.c
arch/powerpc/kernel/head_44x.S

index 6a6e6c71ad6f145bea9f251ede0270d0da451b0d..c790634d946b750ecfa8317888c037e461ec5890 100644 (file)
 #include <asm/cputable.h>
 #include <asm/ppc_asm.h>
 
+_GLOBAL(__setup_cpu_440ep)
+       b       __init_fpu_44x
+_GLOBAL(__setup_cpu_440epx)
+       b       __init_fpu_44x
+
+/* enable APU between CPU and FPU */
+_GLOBAL(__init_fpu_44x)
+       mfspr   r3,SPRN_CCR0
+       /* Clear DAPUIB flag in CCR0 */
+       rlwinm  r3,r3,0,12,10
+       mtspr   SPRN_CCR0,r3
+       isync
+       blr
+
index 8711499f5a0283ebeef2230f5c37e2b1544be70b..94d98190e19a31b283d85bd401a7c910d4a2dc17 100644 (file)
@@ -31,6 +31,8 @@ EXPORT_SYMBOL(cur_cpu_spec);
  * and ppc64
  */
 #ifdef CONFIG_PPC32
+extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
+extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
 extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
 extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
 extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
@@ -1111,6 +1113,7 @@ static struct cpu_spec cpu_specs[] = {
                .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
                .icache_bsize           = 32,
                .dcache_bsize           = 32,
+               .cpu_setup              = __setup_cpu_440ep,
                .platform               = "ppc440",
        },
        {
@@ -1121,6 +1124,7 @@ static struct cpu_spec cpu_specs[] = {
                .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
                .icache_bsize           = 32,
                .dcache_bsize           = 32,
+               .cpu_setup              = __setup_cpu_440ep,
                .platform               = "ppc440",
        },
        { /* 440EPX */
@@ -1131,6 +1135,8 @@ static struct cpu_spec cpu_specs[] = {
                .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
                .icache_bsize           = 32,
                .dcache_bsize           = 32,
+               .cpu_setup              = __setup_cpu_440epx,
+               .platform               = "ppc440",
        },
        { /* 440GRX */
                .pvr_mask               = 0xf0000ffb,
index c6a510bdefd4793d057a314f9b8b3ba8f69dc9ed..864d63fbb2047f4737d9ea978e2e6912b056c45e 100644 (file)
@@ -217,16 +217,6 @@ skpinv:    addi    r4,r4,1                         /* Increment */
        lis     r4,interrupt_base@h     /* IVPR only uses the high 16-bits */
        mtspr   SPRN_IVPR,r4
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
-       /* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */
-       mfspr   r2,SPRN_CCR0
-       lis     r3,0xffef
-       ori     r3,r3,0xffff
-       and     r2,r2,r3
-       mtspr   SPRN_CCR0,r2
-       isync
-#endif
-
        /*
         * This is where the main kernel code starts.
         */