/* Enable an APLL if off */
-static void omap2_clk_fixed_enable(struct clk *clk)
+static int omap2_clk_fixed_enable(struct clk *clk)
{
u32 cval, apll_mask;
cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
if ((cval & apll_mask) == apll_mask)
- return; /* apll already enabled */
+ return 0; /* apll already enabled */
cval &= ~apll_mask;
cval |= apll_mask;
omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
clk->name);
+
+ /*
+ * REVISIT: Should we return an error code if omap2_wait_clock_ready()
+ * fails?
+ */
+ return 0;
}
static void omap2_clk_wait_ready(struct clk *clk)
return -EINVAL;
}
- if (clk->enable_reg == OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
- omap2_clk_fixed_enable(clk);
- return 0;
- }
-
regval32 = cm_read_reg(clk->enable_reg);
regval32 |= (1 << clk->enable_bit);
cm_write_reg(regval32, clk->enable_reg);
return;
}
- if (clk->enable_reg == OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
- omap2_clk_fixed_disable(clk);
- return;
- }
-
regval32 = cm_read_reg(clk->enable_reg);
regval32 &= ~(1 << clk->enable_bit);
cm_write_reg(regval32, clk->enable_reg);
static u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
static void omap2_dpll_recalc(struct clk *clk);
static void omap2_fixed_divisor_recalc(struct clk *clk);
+static int omap2_clk_fixed_enable(struct clk *clk);
+static void omap2_clk_fixed_disable(struct clk *clk);
static long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
static int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
RATE_FIXED | RATE_PROPAGATES,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
+ .enable = &omap2_clk_fixed_enable,
+ .disable = &omap2_clk_fixed_disable,
.recalc = &propagate_rate,
};
RATE_FIXED | RATE_PROPAGATES,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
+ .enable = &omap2_clk_fixed_enable,
+ .disable = &omap2_clk_fixed_disable,
.recalc = &propagate_rate,
};