]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[MIPS] 24K LV: Add core card id.
authorChris Dearman <chris@mips.com>
Fri, 14 Apr 2006 23:31:16 +0000 (00:31 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Thu, 27 Apr 2006 14:13:50 +0000 (15:13 +0100)
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mips-boards/generic/init.c
arch/mips/mips-boards/generic/pci.c
arch/mips/mips-boards/malta/malta_int.c
include/asm-mips/mips-boards/generic.h

index 17dfe6a8cab9b38b9b3620217953c57c6a118406..df4e9473560441bb1b9fcec9038155c4edf61173 100644 (file)
@@ -337,6 +337,7 @@ void __init prom_init(void)
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
        case MIPS_REVISION_CORID_CORE_FPGA3:
+       case MIPS_REVISION_CORID_CORE_24K:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
 
index 1f6f9df74ab22e76292348b50430c96aa24408e4..9337f6c8873acff6a47aee7ee69baab65c986d28 100644 (file)
@@ -198,6 +198,7 @@ void __init mips_pcibios_init(void)
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
        case MIPS_REVISION_CORID_CORE_FPGA3:
+       case MIPS_REVISION_CORID_CORE_24K:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                /* Set up resource ranges from the controller's registers.  */
                MSC_READ(MSC01_PCI_SC2PMBASL, start);
index 64db07d4dbe500d5c3a66355ff1f19c9f6e9ec34..7cc0ba4f553ab2bae354b14fe07983faf47cfb37 100644 (file)
@@ -57,6 +57,7 @@ static inline int mips_pcibios_iack(void)
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
        case MIPS_REVISION_CORID_CORE_FPGA3:
+       case MIPS_REVISION_CORID_CORE_24K:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                MSC_READ(MSC01_PCI_IACK, irq);
                irq &= 0xff;
@@ -143,6 +144,7 @@ void corehi_irqdispatch(struct pt_regs *regs)
         case MIPS_REVISION_CORID_CORE_MSC:
         case MIPS_REVISION_CORID_CORE_FPGA2:
         case MIPS_REVISION_CORID_CORE_FPGA3:
+        case MIPS_REVISION_CORID_CORE_24K:
         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                 ll_msc_irq(regs);
                 break;
@@ -309,6 +311,7 @@ void __init arch_init_irq(void)
         case MIPS_REVISION_CORID_CORE_MSC:
         case MIPS_REVISION_CORID_CORE_FPGA2:
         case MIPS_REVISION_CORID_CORE_FPGA3:
+        case MIPS_REVISION_CORID_CORE_24K:
         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                if (cpu_has_veic)
                        init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
index 25b6ffc266237caec9df04792b5cd2b948fe9ef8..fa8b913cc3e0e0ba262d938ad1d8829df6443ed7 100644 (file)
@@ -67,6 +67,7 @@
 #define MIPS_REVISION_CORID_CORE_FPGA2     7
 #define MIPS_REVISION_CORID_CORE_FPGAR2    8
 #define MIPS_REVISION_CORID_CORE_FPGA3     9
+#define MIPS_REVISION_CORID_CORE_24K       10
 
 /**** Artificial corid defines ****/
 /*